Patent US6243768B1 successfully refreshed from Google Patents.
US6243768B1
Expired / Lapsed
US
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Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
Assignee: Intel Corp
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Filing: 1998-12-10
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Granted: 2001-06-05
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Expires: 2018-12-10
Abstract
Abstract A method and an apparatus for a synchronous DRAM-type memory control is provided that allows continued and accurate data transfer to and from a synchronous DRAM (syncDRAM) memory for special cases where data is not ready to be transferred. In the event that data is not ready to be transferred between a destination device and the syncDRAM, transfer of data is suspended. Concurrently, at the address from which data was not ready to be transferred, the address is latched by a syncDRAM interface that communicates with the system memory control and the syncDRAM memory. In the event of a read cycle, back-to-back read requests are performed until data can be transferred. In the event of a write request, a mask command is asserted to mask out the data address in the syncDRAM until data is ready to be written to the address, wherein the write request is then reasserted. For both read and write cycles, when data is subsequently ready to be transferred, data transfer is resumed at the latched address. This effectively replaces the clock enable functionality and provides cost savings and die size savings.
Inventors
- 👤 Narendra S. Khandekar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 21:12
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/161; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C7/00; G11C7/10; G11C7/1015; G11C7/1018; G11C7/1072; G11C7/22
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
164 words
A method of performing a burst transfer of data between a memory resource and a device, the method including: initiating a burst transfer of data between the memory resource and the device; determining if the burst transfer of data between the memory resource and the device is allowable; if the burst transfer of the data is allowable, then transferring a portion of the data and incrementing an access address to reference a subsequent location in the memory resource; and if the burst transfer of the data is not allowable, then maintaining the access address to reference a current location in the memory resource, performing a sequence of back-to-back operations with respect to the access address, so that each operation of the sequence of operations is with respect to the current location in the memory resource, and maintaining an internal clock of the memory resource operational by maintaining a clock enable signal in an asserted state until the burst transfer of the data becomes allowable.
Claim 2
Independent Claim
164 words
A method of performing a burst transfer of data between a memory resource and a device, the method including: initiating a burst transfer of data between the memory resource and the device; determining if the burst transfer of data between the memory resource and the device is allowable; if the burst transfer of the data is allowable, then transferring a portion of the data and incrementing an access address to reference a subsequent location in the memory resource; and if the burst transfer of the data is not allowable, then maintaining the access address to reference a current location in the memory resource, performing a sequence of back-to-back operations with respect to the access address, so that each operation of the sequence of operations is with respect to the current location in the memory resource, and maintaining an internal clock of the memory resource operational by maintaining a clock enable signal in an asserted state until the burst transfer of the data becomes allowable.
Claim 3
Dependent Claim
21 words
The method of claim 1 including determining whether the data is available for transfer between the memory resource and the device.
Claim 4
Dependent Claim
20 words
The method of claim 1 including determining whether the device is ready to receive the data from the memory resource.
Claim 5
Dependent Claim
20 words
The method of claim 1 including determining whether the memory resource is ready to receive the data from the device.
Claim 6
Dependent Claim
27 words
The method of claim 1 wherein the performing of the sequence of back-to-back operations includes maintaining the access address for each of the sequence of back-to-back operations.
Claim 7
Dependent Claim
22 words
The method of claim 1 including asserting a hold signal to indicate that the burst transfer of the data is not allowable.
Claim 8
Dependent Claim
43 words
The method of claim 1 wherein the burst transfer of the data comprises a read operation from the memory resource, the method including performing a sequence of back-to-back read operations from the access address until the burst transfer of the data becomes allowable.
Claim 9
Dependent Claim
42 words
The method of claim 1 wherein the burst transfer of data comprises a write operation to the memory resource, the method including performing a sequence of back-to-back write operations to the access address until the burst transfer of the data becomes allowable.
Claim 10
Dependent Claim
36 words
The method of claim 1 including masking the access address to prevent data from being written to, or read from, the access address within the memory resource until the burst transfer of the data becomes allowable.
Claim 11
Dependent Claim
173 words
Apparatus for controlling a burst transfer of data between a memory resource and a bus, the apparatus comprising: a controller that initiates the burst transfer of the data and that determines whether the burst transfer of the data is allowable; a memory interface, if the burst transfer of the data is allowable, to transfer a portion of the data and to increment an access address to reference a subsequent location in the memory resource and that, if the burst transfer of the data is not allowable, to maintain the access address to reference a current location in the memory resource and to perform a sequence of back-to-back operations with respect to the access address, so that each operation of the sequence of back-to-back operations is with respect to the current location in the memory resource, until the burst transfer of the data does become allowable; and clock enable circuitry that maintains a clock enable signal to the memory resource in an asserted state if the burst transfer of the data is not allowable.
Claim 12
Dependent Claim
173 words
Apparatus for controlling a burst transfer of data between a memory resource and a bus, the apparatus comprising: a controller that initiates the burst transfer of the data and that determines whether the burst transfer of the data is allowable; a memory interface, if the burst transfer of the data is allowable, to transfer a portion of the data and to increment an access address to reference a subsequent location in the memory resource and that, if the burst transfer of the data is not allowable, to maintain the access address to reference a current location in the memory resource and to perform a sequence of back-to-back operations with respect to the access address, so that each operation of the sequence of back-to-back operations is with respect to the current location in the memory resource, until the burst transfer of the data does become allowable; and clock enable circuitry that maintains a clock enable signal to the memory resource in an asserted state if the burst transfer of the data is not allowable.
Claim 13
Dependent Claim
37 words
The apparatus of claim 10 wherein the controller asserts a hold signal to indicate that the burst transfer is not allowable, and de-asserts the hold signal to indicate that the burst transfer of the data is allowable.
Claim 14
Dependent Claim
43 words
The apparatus of claim 10 wherein the burst transfer of the data comprises a read operation from the memory resource, the memory interface performing a sequence of back-to-back read operations from the access address until the burst transfer of the data becomes allowable.
Claim 15
Dependent Claim
42 words
The apparatus of claim 10 wherein the burst transfer of the data comprises a write operation to the memory resource, the interface performing a sequence of back-to-back write operations to the access address until the burst transfer of the data becomes allowable.
Claim 16
Dependent Claim
41 words
The apparatus of claim 13 wherein the memory interface includes a mask generator that masks the access address to prevent data from being written to the access address within the memory resource before the burst transfer of the data becomes allowable.
Claim 17
Dependent Claim
24 words
The apparatus of claim 10 wherein the memory interface includes address incrementing logic that increments the access address if the burst transfer is allowable.
Claim 18
Dependent Claim
175 words
A memory subsystem for use in a computer system, the memory arrangement comprising: a memory; a controller, coupled to the memory, that initiates a burst transfer of data between the memory and a bus, determines whether the burst transfer of the data is allowable, and maintains a clock enable signal propagated to the memory in an asserted state if the burst transfer is not allowable to thereby maintain an internal clock mechanism of the memory active; and a memory interface, if the burst transfer is allowable, to transfer a portion of the data and increment an access address to reference a subsequent location in the memory resource and that, if the burst transfer is not allowable, to maintain the access address to reference a current location in the memory resource and to perform a sequence of back-to-back operations with respect to the access address, so that each operation of the sequence of back-to-back operations is with respect to the current location in the memory resource, until the burst transfer of the data does become allowable.
Claim 19
Dependent Claim
175 words
A memory subsystem for use in a computer system, the memory arrangement comprising: a memory; a controller, coupled to the memory, that initiates a burst transfer of data between the memory and a bus, determines whether the burst transfer of the data is allowable, and maintains a clock enable signal propagated to the memory in an asserted state if the burst transfer is not allowable to thereby maintain an internal clock mechanism of the memory active; and a memory interface, if the burst transfer is allowable, to transfer a portion of the data and increment an access address to reference a subsequent location in the memory resource and that, if the burst transfer is not allowable, to maintain the access address to reference a current location in the memory resource and to perform a sequence of back-to-back operations with respect to the access address, so that each operation of the sequence of back-to-back operations is with respect to the current location in the memory resource, until the burst transfer of the data does become allowable.
Claim 20
Dependent Claim
25 words
The memory subsystem of claim 16 wherein the controller determines whether the burst transfer of the data between the memory and the bus is allowable.
Claim 21
Dependent Claim
23 words
The memory subsystem of claim 17 wherein the controller determines whether the data is available for transfer between the memory and the bus.
References Cited (Backward Citations)
US4792926A
Cited
US5134699A
Cited
US5159679A
Cited
US5268865A
Cited
US5526513A
Cited
US5530944A
Cited
US5390149A
Cited
US5321651A
Cited
US5469577A
Cited
US5586286A
Cited
US5640517A
Cited
US5640527A
Cited
WO1995006287A1
Cited
US5897667A
Cited
US5941960A
Cited
US5519872A
Cited
US5513148A
Cited
US5661695A
Cited
US5657287A
Cited
US5600605A
Cited
US5918072A
Cited
US5809260A
Cited
US5715476A
Cited
US5926828A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-06-04 | 2004-12-04 | 2005-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-06-04 | 2008-12-04 | 2009-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-06-04 | 2012-12-04 | 2013-06-05 | $7700.00 | Window Closed / Lapsed |