US5897667A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for transferring data received from a first bus in a non-burst manner to a second bus in a burst manner
Assignee: Intel Corp
•
Filing: 1996-11-22
•
Granted: 1999-04-27
•
Expires: 2016-11-22
Abstract
Abstract A bridge logic takes non-burst write cycles that appear one at a time as an address followed by an associated data word on a first bus, detects consecutive addresses, and uses this information to create burst cycles on a second bus that has protocols that allow burst cycles such as a Peripheral Component Interconnect (PCI) bus.
Inventors
- 👤 Mark W. Miller
- 👤 Ali S. Oztaskin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 21:19
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027
Claims Analysis
Total Claims: 59
Claim 1
Independent Claim
118 words
A system comprising: a first bus which supports non-burst write cycles; a processor, coupled to the first bus, to place a plurality of non-burst write cycles on the first bus; a second bus; and a bridge coupled to the first bus and the second bus, wherein the bridge includes, a plurality of data buffers to store data from the plurality of non-burst write cycles, a comparator to identify two or more write cycles of the plurality of non-burst write cycles which are to consecutive addresses, and control logic, coupled to the plurality of data buffers and the comparator, to transfer the data of the two or more writes cycles to the second bus in a burst write cycle.
Claim 2
Independent Claim
118 words
A system comprising: a first bus which supports non-burst write cycles; a processor, coupled to the first bus, to place a plurality of non-burst write cycles on the first bus; a second bus; and a bridge coupled to the first bus and the second bus, wherein the bridge includes, a plurality of data buffers to store data from the plurality of non-burst write cycles, a comparator to identify two or more write cycles of the plurality of non-burst write cycles which are to consecutive addresses, and control logic, coupled to the plurality of data buffers and the comparator, to transfer the data of the two or more writes cycles to the second bus in a burst write cycle.
Claim 3
Dependent Claim
70 words
The system of claim 1, wherein the bridge also includes: a consecutive flag, coupled to the control logic, which corresponds to a first data buffer of the plurality of data buffers and which indicates whether the data in the first data buffer is from a write cycle of the plurality of non-burst write cycles which was sequential to an immediately preceding write cycle of the plurality of non-burst write cycles.
Claim 4
Dependent Claim
56 words
The system of claim 2, wherein the first bus includes an address bus, wherein the comparator is coupled to the address bus and to a consecutive address register, and wherein the comparator is to set the consecutive flag responsive to an address on the address bus being equal to an address in the consecutive address register.
Claim 5
Dependent Claim
64 words
The system of claim 1, wherein the bridge further includes: a plurality of address buffers, coupled to the comparator, to store a plurality of addresses corresponding to the plurality of non-burst write cycles, wherein the comparator is to identify the two or more write cycles concurrent with the addresses of the plurality of non-burst write cycles being stored in the plurality of address buffers.
Claim 6
Dependent Claim
151 words
The system of claim 1, wherein the bridge further includes a first signal line and a second signal line coupling the comparator and the control logic, wherein assertion of a first signal on the first signal line indicates data from at least one of the two or more write cycles remains in the plurality of data buffers, wherein the comparator is to assert the first signal in response to data from at least one of the two or more write cycles remaining in the plurality of data buffers, wherein assertion of a second signal on the second signal line indicates data from at least two of the two or more write cycles remains in the plurality of data buffers, and wherein the comparator is to assert the second signal in response to data from at least two of the two or more write cycles remaining in the plurality of data buffers.
Claim 7
Dependent Claim
50 words
The system of claim 1, wherein the bridge further includes a plurality of posted flags corresponding to the plurality of data buffers, wherein each posted flag indicates whether the data in the corresponding data buffer is from a write cycle of the plurality of non-burst write cycles which is postable.
Claim 8
Dependent Claim
46 words
The system of claim 1, wherein the bridge further includes: a plurality of address buffers, coupled to the comparator, to store each address from the plurality of non-burst write cycles, and wherein at least two of the plurality of non-burst write cycles are to non-sequential addresses.
Claim 9
Dependent Claim
15 words
The system of claim 1, wherein the plurality of data buffers comprises four data buffers.
Claim 10
Dependent Claim
18 words
The system of claim 1, wherein the plurality of data buffers comprises less than ten thousand data buffers.
Claim 11
Dependent Claim
34 words
The system of claim 1, wherein the comparator is implemented in a first chip and the plurality of data buffers are implemented in a second chip which is physically separate from the first chip.
Claim 12
Dependent Claim
24 words
The system of claim 1, wherein the comparator includes an incrementer for incrementing an address from the plurality of non-burst write cycles by one.
Claim 13
Dependent Claim
46 words
The system of claim 1, wherein the comparator includes equality comparison logic to determine whether an address of a first write cycle of the plurality of non-burst write cycles is sequential to an address of a second write cycle of the plurality of non-burst write cycles.
Claim 14
Dependent Claim
16 words
The system of claim 1, wherein the second bus is a Peripheral Component Interconnect (PCI) bus.
Claim 15
Independent Claim
82 words
An apparatus comprising: first control logic to receive data in a plurality of non-burst write cycles; a plurality of data buffers, coupled to the first control logic, to store the data; comparison logic to identify two or more write cycles of the plurality of non-burst write cycles which are to sequential addresses; and second control logic, coupled to the plurality of data buffers, to output the data of the two or more write cycles on a bus in a burst write cycle.
Claim 16
Independent Claim
82 words
An apparatus comprising: first control logic to receive data in a plurality of non-burst write cycles; a plurality of data buffers, coupled to the first control logic, to store the data; comparison logic to identify two or more write cycles of the plurality of non-burst write cycles which are to sequential addresses; and second control logic, coupled to the plurality of data buffers, to output the data of the two or more write cycles on a bus in a burst write cycle.
Claim 17
Dependent Claim
32 words
The apparatus of claim 14, further comprising: a plurality of address buffers, coupled to the first control logic, to store a plurality of addresses corresponding to the plurality of non-burst write cycles.
Claim 18
Dependent Claim
71 words
The apparatus of claim 14, further comprising: a consecutive address register to store a previous address received by the first control logic incremented by one; and a comparator, coupled to the consecutive address register, to set a consecutive address flag corresponding to a first address of a plurality of addresses corresponding to the plurality of non-burst write cycles in response to the first address equaling the previous address incremented by one.
Claim 19
Dependent Claim
28 words
The apparatus of claim 16, wherein the previous address incremented by one corresponds to an address of the plurality of addresses received immediately previous to the first address.
Claim 20
Dependent Claim
63 words
The apparatus of claim 14, further comprising: a plurality of address buffers, coupled to the first control logic, to store a plurality of addresses corresponding to the plurality of non-burst write cycles, wherein the comparison logic is to identify the two or more write cycles as the addresses of the plurality of non-burst write cycles are stored in the plurality of address buffers.
Claim 21
Dependent Claim
152 words
The apparatus of claim 14, further comprising a first signal line and a second signal line coupling the comparison logic and the second control logic, wherein assertion of a first signal on the first signal line indicates data from at least one of the two or more write cycles remains in the plurality of data buffers, wherein the comparison logic is to assert the first signal in response to data from at least one of the two or more write cycles remaining in the plurality of data buffers, wherein assertion of a second signal on the second signal line indicates data from at least two of the two or more write cycles remains in the plurality of data buffers, and wherein the comparison logic is to assert the second signal in response to data from at least two of the two or more write cycles remaining in the plurality of data buffers.
Claim 22
Dependent Claim
47 words
The apparatus of claim 14, further comprising a plurality of posted flags corresponding to the plurality of data buffers, wherein each posted flag indicates whether the data in the corresponding data buffer is from a write cycle of the plurality of non-burst write cycles which is postable.
Claim 23
Dependent Claim
60 words
The apparatus of claim 14, further comprising a plurality of consecutive flags corresponding to the plurality of data buffers, wherein each consecutive flag indicates whether the data in the corresponding data buffer is from a write cycle of the plurality of non-burst write cycles which was sequential to an immediately preceding write cycle of the plurality of non-burst write cycles.
Claim 24
Dependent Claim
35 words
The apparatus of claim 14, wherein the comparison logic is implemented in a first chip and the plurality of data buffers are implemented in a second chip which is physically separate from the first chip.
Claim 25
Dependent Claim
25 words
The apparatus of claim 14, wherein the comparison logic includes an incrementer for incrementing an address from the plurality of non-burst write cycles by one.
Claim 26
Dependent Claim
47 words
The apparatus of claim 14, wherein the comparison logic includes an equality comparator to determine whether an address of a first write cycle of the plurality of non-burst write cycles is sequential to an address of a second write cycle of the plurality of non-burst write cycles.
Claim 27
Dependent Claim
15 words
The apparatus of claim 14, wherein the plurality of data buffers comprises four data buffers.
Claim 28
Dependent Claim
18 words
The apparatus of claim 14, wherein the plurality of data buffers comprises less than ten thousand data buffers.
Claim 29
Dependent Claim
44 words
The apparatus of claim 14, further comprising a plurality of address buffers, coupled to the comparison logic, to store each address from the plurality of non-burst write cycles, and wherein at least two of the plurality of non-burst write cycles are to non-sequential addresses.
Claim 30
Independent Claim
63 words
A method comprising the steps of: receiving a plurality of address/data pairs from a first bus, wherein each of the address/data pairs appears on the first bus in a non-burst manner; detecting two address/data pairs of the plurality of address/data pairs which have sequential addresses; and transferring the data of the two address/data pairs to a second bus in a burst write manner.
Claim 31
Independent Claim
63 words
A method comprising the steps of: receiving a plurality of address/data pairs from a first bus, wherein each of the address/data pairs appears on the first bus in a non-burst manner; detecting two address/data pairs of the plurality of address/data pairs which have sequential addresses; and transferring the data of the two address/data pairs to a second bus in a burst write manner.
Claim 32
Dependent Claim
106 words
A bus bridge comprising: a plurality of data buffers to store data received from a first bus as part of a plurality of non-burst write cycles, wherein each of the plurality of non-burst write cycles appears on the first bus in a non-burst manner as an address and an associated data word; comparison logic to detect two consecutive addresses from the plurality of non-burst write cycles; and a Peripheral Component Interconnect (PCI) bus interface, coupled to the plurality of data buffers and to the comparison logic, to transfer the data words associated with the two consecutive addresses to a PCI bus as a burst write cycle.
Claim 33
Dependent Claim
106 words
A bus bridge comprising: a plurality of data buffers to store data received from a first bus as part of a plurality of non-burst write cycles, wherein each of the plurality of non-burst write cycles appears on the first bus in a non-burst manner as an address and an associated data word; comparison logic to detect two consecutive addresses from the plurality of non-burst write cycles; and a Peripheral Component Interconnect (PCI) bus interface, coupled to the plurality of data buffers and to the comparison logic, to transfer the data words associated with the two consecutive addresses to a PCI bus as a burst write cycle.
Claim 34
Dependent Claim
24 words
The bus bridge of claim 29, further comprising: a plurality of address buffers to store the addresses from the plurality of non-burst write cycles.
Claim 35
Dependent Claim
76 words
The bus bridge of claim 30, further comprising: an increment logic to generate, upon receipt of a first address from the first bus, a consecutive address value; and an equality comparator to compare a second address received from the first bus to the consecutive address value, and to set a consecutive flag, corresponding to the second address, indicating that the first and second addresses are consecutive, responsive to the second address equaling the consecutive address value.
Claim 36
Independent Claim
54 words
A method comprising the steps of: receiving a plurality of non-burst address/data pairs from a first bus; detecting two or more address/data pairs of the plurality of non-burst address/data pairs which have consecutive addresses; and transferring the data of the two or more address/data pairs to a second bus in a burst write cycle.
Claim 37
Independent Claim
54 words
A method comprising the steps of: receiving a plurality of non-burst address/data pairs from a first bus; detecting two or more address/data pairs of the plurality of non-burst address/data pairs which have consecutive addresses; and transferring the data of the two or more address/data pairs to a second bus in a burst write cycle.
Claim 38
Dependent Claim
46 words
The method of claim 32, wherein the step of transferring the data of the two or more address/data pairs comprises the step of transferring the data of the two or more address/data pairs to the second bus responsive to a buffer empty signal being sampled inactive.
Claim 39
Dependent Claim
22 words
The method of claim 32, further comprising the step of: storing the data of each of the plurality of non-burst address/data pairs.
Claim 40
Dependent Claim
84 words
The method of claim 32, wherein the step of detecting the two or more address/data pairs includes the steps of: generating a consecutive address value based on a first non-burst address/data pair received from the first bus; receiving a second non-burst address/data pair from the first bus; comparing the address of the second non-burst address/data pair to the consecutive address value; and setting a consecutive flag indicating whether the address of the second non-burst address/data pair is the same as the consecutive address value.
Claim 41
Dependent Claim
110 words
The method of claim 32, further comprising the steps of: identifying whether data from at least one of the two or more address/data pairs is remaining to be transferred to the second bus; identifying whether data from at least two of the two or more address/data pairs is remaining to be transferred to the second bus; and providing at least one signal on the second bus based on whether at least one of the two or more address/data pairs is remaining to be transferred to the second bus and on whether at least two of the two or more address/data pairs is remaining to be transferred to the second bus.
Claim 42
Dependent Claim
36 words
The method of claim 32, further comprising the step of setting a posted flag corresponding to an address of one of the plurality of non-burst address/data pairs in response to the one address/data pair being postable.
Claim 43
Dependent Claim
49 words
The method of claim 32, further comprising the step of setting a consecutive flag corresponding to one of the plurality of non-burst address/data pairs in response to the address of the one address/data pair being sequential to an immediately preceding address/data pair of the plurality of non-burst address/data pairs.
Claim 44
Dependent Claim
35 words
The method of claim 32, further comprising the step of storing each address of the plurality of non-burst address/data pairs, wherein at least two of the plurality of non-burst address/data pairs are to non-consecutive addresses.
Claim 45
Dependent Claim
75 words
The method of claim 32, further comprising the step of placing the plurality of non-burst address/data pairs into a plurality of address buffers upon receiving the plurality of non-burst address/data pairs from the first bus, wherein the step of detecting two or more address/data pairs comprises the step of detecting the two or more address/data pairs which have consecutive addresses as the plurality of non-burst address/data pairs are placed into the plurality of address buffers.
Claim 46
Dependent Claim
66 words
The method of claim 32, further comprising the step of storing data of the plurality of non-burst address/data pairs in a plurality of data buffers, wherein the step of storing data in the plurality of data buffers occurs on a first chip and the step of detecting the two or more address/data pairs occurs on a second chip which is physically separate from the first chip.
Claim 47
Dependent Claim
33 words
The method of claim 32, wherein the step of detecting the two or more address/data pairs includes the step of incrementing the address of one of the plurality of address/data pairs by one.
Claim 48
Dependent Claim
44 words
The method of claim 32, wherein the step of detecting the two or more address/data pairs includes the step of using an equality comparator to determine whether an address of a first address/data pair is sequential to an address of a second address/data pair.
Claim 49
Dependent Claim
28 words
The method of claim 32, further comprising the step of storing the data of each of the plurality of non-burst address/data pairs in one of four data buffers.
Claim 50
Dependent Claim
31 words
The method of claim 32, further comprising the step of storing the data of each of the plurality of non-burst address/data pairs in one of at least ten thousand data buffers.
Claim 51
Independent Claim
57 words
An apparatus comprising: means for receiving a plurality of non-burst address/data pairs from a first bus; means for detecting two or more address/data pairs of the plurality of non-burst address/data pairs which have consecutive addresses; and means for transferring the data of the two or more address/data pairs to a second bus in a burst write cycle.
Claim 52
Independent Claim
57 words
An apparatus comprising: means for receiving a plurality of non-burst address/data pairs from a first bus; means for detecting two or more address/data pairs of the plurality of non-burst address/data pairs which have consecutive addresses; and means for transferring the data of the two or more address/data pairs to a second bus in a burst write cycle.
Claim 53
Dependent Claim
36 words
The apparatus of claim 46, wherein the means for transferring comprises means for transferring the data of the two or more address/data pairs to the second bus responsive to a buffer empty signal being sampled inactive.
Claim 54
Dependent Claim
21 words
The apparatus of claim 46, further comprising: means for storing the data of each of the plurality of non-burst address/data pairs.
Claim 55
Dependent Claim
95 words
The apparatus of claim 48, wherein the means for detecting includes: means for generating a consecutive address value based on a first non-burst address/data pair received from the first bus; means for receiving a second non-burst address/data pair from the first bus; means for comparing the address of the second non-burst address/data pair to the consecutive address value; and means for setting a consecutive flag corresponding to the second non-burst address/data pair responsive to the means for comparing indicating the address of the second non-burst address/data pair is the same as the consecutive address value.
Claim 56
Dependent Claim
114 words
In a bus bridge coupled to a first bus and a Peripheral Component Interconnect (PCI) bus, wherein the bus bridge includes a plurality of data buffers and control logic to transfer data from the plurality of data buffers to the PCI bus, a method comprising the steps of: receiving a plurality of address/data pairs from the first bus in a non-burst manner; detecting two or more address/data pairs of the plurality of address/data pairs which have sequential addresses; storing the data of the two or more address/data pairs in the plurality of data buffers; and transferring the data of the two or more address/data pairs to the PCI bus in a burst write manner.
Claim 57
Dependent Claim
114 words
In a bus bridge coupled to a first bus and a Peripheral Component Interconnect (PCI) bus, wherein the bus bridge includes a plurality of data buffers and control logic to transfer data from the plurality of data buffers to the PCI bus, a method comprising the steps of: receiving a plurality of address/data pairs from the first bus in a non-burst manner; detecting two or more address/data pairs of the plurality of address/data pairs which have sequential addresses; storing the data of the two or more address/data pairs in the plurality of data buffers; and transferring the data of the two or more address/data pairs to the PCI bus in a burst write manner.
Claim 58
Dependent Claim
42 words
The method of claim 50, wherein the step of transferring the data of the two or more address/data pairs comprises the step of bursting the data of the two or more address/data pairs to a target agent coupled to the PCI bus.
Claim 59
Dependent Claim
93 words
The method of claim 50, wherein the step of detecting the two or more address/data pairs includes the steps of: generating a consecutive address value based on a first address/data pair of the plurality of address/data pairs; receiving a second address/data pair from the first bus; comparing the address of the second address/data pair to the consecutive address value; and setting a consecutive flag corresponding to the address of the second address/data pair responsive to the comparing indicating the address of the second address/data pair is the same as the consecutive address value.
References Cited (Backward Citations)
US3818461A
Cited
US3999168A
Cited
US4031519A
Cited
US4032899A
Cited
US4052699A
Cited
US4868734A
Cited
US4965801A
Cited
US5239638A
Cited
EP0416281A2
Cited
US5075846A
Cited
US5197144A
Cited
US5410656A
Cited
US5325499A
Cited
US5241630A
Cited
US5289584A
Cited
US5269005A
Cited
US5333276A
Cited
US5392407A
Cited
US5483640A
Cited
US5448310A
Cited
EP0627688A1
Cited
EP0629956A2
Cited
US5550989A
Cited
US5564026A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-26 | 2002-10-26 | 2003-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-26 | 2006-10-26 | 2007-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-26 | 2010-10-26 | 2011-04-27 | $7700.00 | Window Closed / Lapsed |