Data buffer

Claim 2

Data buffer for transferring data from a first data bus (A) to a second data bus (B), of a Data Processor System, characterized by a dual port storage mechanism having a storage array (26) and two independent ports with seperate data, address and control lines; write circuitry (33) coupled to one of the independent ports for receiving data from the first data bus and storing it into a first portion of the storage array; read circuitry (40) coupled to the other of the independent ports for reading data from a second portion of the storage array and supplying it to the second data bus, such reading from the second portion occurring simultaneously with the storing of data into the first portion of the storage array; and mode control logic (21, 60, 61) coupled to the write circuitry and to the read circuitry for interchanging the functions of the first and second portions of the storage array so that data from the first data bus is stored into the second portion while data is being read from the first portion and supplied to the second data bus.

Claim 3

Data buffer in accordance with claim 1, characterized in that the functions of the first and second portions of the storage array are interchanged back and forth from time to time, an interchange occurring when one storage array portion becomes full of data and the other storage array portion becomes empty of data.

Claim 4

Data buffer in accordance with claim 1, characterized by multiplex circuitry (47, 54) for selectively enabling one of the following data transfer modes: (1) first data bus coupled to the write circuitry and second data bus coupled to the read circuitry, and (2) second data bus coupled to the write circuitry and first data bus coupled to the read circuitry; whereby the data buffer (25) enables bidirectional operations so that data may be transferred from the first data bus to the second data bus or vice versa during any given data transfer operation.

Claim 5

Data buffer in accordance with claim 1, characterized in that the data is transferred from the first data bus (A) to the second data bus (B) in sequential bursts, with each burst containing at most a maximum predetermined amount of data; and that the data buffer (25) further includes programmable burst length circuitry coupled to the write circuitry for limiting the maximum amount of data stored into the first and second portions of the storage array to make such amount equal to the maximum predetermined amount for the data bursts.

Claim 6

Data buffer in accordance with claim 1, characterized by two-state latch circuitry having a pair of opposite polarity output lines, one of which is connected to the most significant bit address line for one port of the dual port storage mechanism and the other of which is connected to the most significant bit address line for the other port of the dual port storage mechanism, thereby eliminating contention by preventing both write and read access to the same portion of the storage array at any given moment; and by full/empty logic circuitry coupled to the write circuitry and to the read circuitry for switching the state of the two-state latch circuitry when one storage array portion becomes full of data and the other storage array portion becomes empty of data.

Claim 7

Data buffer in accordance with claim 1, characterized in that the write circuitry includes data input circuitry for supplying data from the first data bus to the data lines of a first port of the dual port storage mechanism, input address counter circuitry for supplying a multibit address to the address lines of the first port and strobe circuitry for supplying strobe signals to a control line of the first port for writing data into the storage array and to a count update line of the input address counter circuitry for updating the count value therein; and that the read circuitry includes data output circuitry for supplying data from the data lines of a second port of the dual port storage mechanism to the second data bus, output address counter circuitry for supplying a multibit address to the address lines of the second port and strobe circuitry for supplying strobe signals to a control line of the second port for reading data from the storage array and to a count update line of the output address counter circuitry for updating the count value therein.

Claim 8

Data buffer in accordance with claim 6, characterized in that the input address counter circuitry supplies the multibit address to the address lines of the first port with the exception of the most significant bit address line of the first port; that the output address counter circuitry supplies the multibit address to the address lines of the second port with the exception of the most significant bit address line of the second port; that the mode control logic includes two-state latch circuitry having a pair of opposite polarity output lines, one of which is connected to the most significant bit address line for the first port and the other of which is connected to the most significant bit address line of the second port, thereby eliminating contention by preventing both write and read access to the same portion of the storage array at any given moment; and that the mode control logic further includes full/empty logic circuitry coupled to the input address counter circuitry and to the output address counter circuitry for switching the state of the two-state latch circuitry when one storage array portion becomes full of data and the other storage array portion becomes empty of data.

Claim 9

Data buffer in accordance with claim 7, characterized by multiplex circuitry for selectively enabling one of the following data transfer modes: (1) first data bus coupled to the data input circuitry and second data bus coupled to the data output circuitry, and (2) second data bus coupled to the data input circuitry and first data bus coupled to the data output circuitry; whereby the data buffer enables bidirectional operations so that data may be transferred from the first data bus to the second data bus or vice versa during any given data transfer operation.

Claim 10

Data buffer as set forth in one of claims 1 to 8, characterized by a plurality of dual port storage mechanisms each having a storage array and two independent ports with seperate data, address and control lines; write circuitry coupled to a first independent port of each dual port storage mechanism for receiving data from one of the data buses and storing it into first portions of the different storage arrays; read circuitry coupled to a second independent port of each dual port storage mechanism for reading data from second portions of the different storage arrays and supplying it to the other of the data buses, such reading from the second portions occurring simultaneously with the storing of data into the first portions of the storage arrays; and by mode control logic coupled to the write circuitry and to the read circuitry for interchanging the functions of the first and second portions of the storage arrays so that data from the one data bus is stored into the second portions while data is being read from the first portions and supplied to the other data bus.

Claim 11

Data buffer as set forth in claim 1 or 9 for transferring data from a wider data bus to a narrower data bus, characterized by a plurality of dual port storage mechanisms each having a storage array and two independent ports with seperate data, address and control lines; write circuitry coupled to a first independent port of each dual port storage mechanism for receiving data from the wider data bus and simultaneously storing different parts of it into first portions of the different storage arrays; read circuitry coupled to a second independent port of each dual port storage mechanism for reading data from second portions of the different storage arrays and sequentially supplying data from different ones of the second portions to the narrower data bus, such reading from the second portions occurring simultaneously with the storing of data into the first portions of the storage arrays; and mode control logic coupled to the write circuitry and to the read circuitry for interchanging the functions of the first and second portions of the storage arrays so that data from the wider data bus is stored into the second portions while data is being read from the first portions and supplied to the narrower data bus.

Claim 12

Data buffer in accordance with claim 10, characterized in that the functions of the first and second portions of the storage arrays are interchanged back and forth from time to time, an interchange occurring when the first portions become full of data and the second portions become empty of data and vice versa.

Claim 13

Data buffer as set forth in claim 1 or 9 for transferring data from a narrower data bus to a wider data bus, characterized by a plurality of dual port storage mechanisms each having a storage array and two independent ports with seperate data, address and control lines; write circuitry coupled to a first independent port of each dual port storage mechanism for receiving data from the narrower data bus and storing it into first portions of the different storage arrays, different sequential segments of such data being sequentially stored into different ones of the first portions; read circuitry coupled to a second independent port of each dual port storage mechanism for simultaneously reading data from second portions of the different storage arrays and simultaneously supplying it to the wider data bus, such reading from the second portions occurring simultaneously with the storing of data into the first portions of the storage arrays; and mode control logic coupled to the write circuitry and to the read circuitry for interchanging the functions of the first and second portions of the storage arrays so that data from the narrower data bus is stored into the second portions while data is being read from the first portions and supplied to the wider data bus.

Claim 14

Data buffer in accordance with claim 12, characterized in that the functions of the first and second portions of the storage arrays are interchanged back and forth from time to time, an interchange occurring when the first portions become full of data and the second portions become empty of data and vice versa.

Claim 15

Data buffer as set forth in claim 1 or 9 for transferring data from a wider data bus to a narrower data bus or vice versa, characterized by a plurality of dual port storage mechanisms each having a storage array and two independent ports with seperate data, address and control lines; write circuitry coupled to a first independent port of each dual port storage mechanism for receiving data from one of the data buses and storing it into first portions of the different storage arrays; read circuitry coupled to a second independent port of each dual port storage mechanism for reading data from second portions of the different storage arrays and supplying it to the other of the data buses, such reading from the second portions occurring simultaneously with the storing of data into the first portions of the storage arrays; mode control logic coupled to the write circuitry and to the read circuitry for interchanging the functions of the first and second portions of the storage arrays so that data from the one data bus is stored into the second portions while data is being read from the first portions and supplied to the other data bus; and the write circuitry including data input multiplexing circuitry for selectively enabling one of the following data transfer modes: (1) simultaneous transfer of data from the wider data bus to the first port data lines of all of the dual port storage mechanisms, and (2) transfer of data from the narrower data bus to the different sets of dual port storage mechanism first port data lines one set at a time in a sequential manner.

Claim 16

Data buffer in accordance with claim 14, characterized in that the read circuitry includes data output multiplexing circuitry for selectively enabling one of the following data transfer modes: (1) simultaneous transfer of data from the second port data lines of all of the dual port storage mechanisms to the wider data bus, and (2) transfer of data from the different sets of dual port storage mechanism second port data lines one set at a time in a sequential manner to the narrower data bus.

Claim 17

Data buffer in accordance with claim 15, characterized by control circuitry for coordinating the data transfer modes of the data input multiplexing circuitry and the data output multiplexing circuitry for causing the former to select mode (1) and the latter to select mode (2) and vice versa.

Claim 18

Data buffer in accordance with claim 16, characterized in that the functions of the first and second portions of the storage arrays are interchanged back and forth from time to time, an interchange occurring when the first portions become full of data and the second portions become empty of data and vice versa.

Claim 19

Data buffer in accordance with claim 16, characterized in that the data is transferred from one data bus to the other data bus in sequential bursts, with each burst containing at most a maximum predetermined amount of data; and the data buffer mechanism further includes programmable burst length circuitry coupled to the write circuitry for limiting the maximum amount of data stored into the first and second portions of the storage arrays to make such amount equal to the maximum predetermined amount for the data bursts.

Claim 20

Data buffer in accordance with claim 16, characterized by two-state latch circuitry having a pair of opposite polarity output lines, one of which is connected to the most significant bit address line of each first port of the dual port storage mechanisms and the other of which is connected to the most significant bit address line of each second port of the dual port storage mechanisms, thereby eliminating contention by preventing both write and read access to the same portions of the storage arrays at any given moment; and full/empty logic circuitry coupled to the write circuitry and to the read circuitry for switching the state of the two-state latch circuitry when the first storage array portions become full of data and the second storage array portions become empty of data and vice versa.

Claim 21

Data buffer as set forth in one of the claims 1-19, characterized by first and second storage arrays; write circuitry for receiving data from the first data bus and storing it into the first and second storage arrays such that even numbered data segments are stored in one storage array and odd numbered data segments are stored in the other storage array; and read circuitry for reading data from the first and second storage arrays and supplying it to the second data bus, such read circuitry including access circuitry for accessing the first and second storage arrays in an alternating manner for reading out and making available successive data segments in a sequential manner and including data output multiplexing circuitry for alternately transferring data segments from the first and second storage arrays to the second data bus, such transferring being offset relative to the accessing such that one data segment is transferred to the second data bus while the next data segment is being accessed from its storage array.