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US6239640B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Double edge trigger d-type flip-flop

Assignee: Silicon Integrated Systems Corp
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Filing: 1999-04-06
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Granted: 2001-05-29
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Expires: 2019-04-06
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Abstract

Abstract The present invention provides a double edge trigger D-type flip-flop which can be both triggered at the rising edge and falling edge of a clock. That is to say, the double edge trigger D-type flip-flop of the present invention can access data twice in a clock cycle. Therefore, the double edge trigger D-type flip-flop of the present invention is capable of providing a double accessed data amount than that of a conventional rising (or falling) edge trigger D-type flip-flop, thereby significantly increasing the efficiency of the system.

Inventors

  • 👤 Stanley Liao
  • 👤 Horng-Jyh Liu
  • 👤 Hsing-Yi Chen

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 17:23
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K3/01; H03K3/012

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 156 words
A double edge trigger flip-flop, comprising at least two inputs and at least three latches, wherein a first input and a second input are respectively coupled to a first tri-state inverter controlled by a clock control signal and a second tri-state inverter controlled by an inverted clock control signal, outputs of the first tri-state inverter and the second tri-state inverter are respectively coupled to a first latch and a second latch, outputs of the first latch and the second latch are respectively coupled to a third tri-state inverter controlled by the clock control signal and a fourth tri-state inverter controlled by the inverted clock control signal, outputs of the third tri-state inverter and the fourth tri-state inverter are respectively coupled to a first input and a second input of a third latch, a first output and a second output of the third latch are respectively an output and inverted output of the double edge trigger flip-flop.
Claim 2
Dependent Claim 156 words
A double edge trigger flip-flop, comprising at least two inputs and at least three latches, wherein a first input and a second input are respectively coupled to a first tri-state inverter controlled by a clock control signal and a second tri-state inverter controlled by an inverted clock control signal, outputs of the first tri-state inverter and the second tri-state inverter are respectively coupled to a first latch and a second latch, outputs of the first latch and the second latch are respectively coupled to a third tri-state inverter controlled by the clock control signal and a fourth tri-state inverter controlled by the inverted clock control signal, outputs of the third tri-state inverter and the fourth tri-state inverter are respectively coupled to a first input and a second input of a third latch, a first output and a second output of the third latch are respectively an output and inverted output of the double edge trigger flip-flop.
Claim 3
Dependent Claim 164 words
A double edge trigger flip-flop, comprising at least two inputs and at least three latches, wherein a first input and a second input are respectively coupled to a first tri-state inverter controlled by a clock control signal and a second tri-state inverter controlled by an inverted clock control signal, outputs of the first tri-state inverter and the second tri-state inverter are respectively coupled to a first latch and a second latch, outputs of the first latch and the second latch are respectively coupled to a third tri-state inverter controlled by the clock control signal and a fourth tri-state inverter controlled by the inverted clock control signal, outputs of the third tri-state inverter and the fourth tri-state inverter are respectively coupled to a first input and a second input of a third latch, wherein the third latch consists of two inverters, a first output and a second output of the third latch are respectively an output and inverted output of the double edge trigger flip-flop.
Claim 4
Dependent Claim 164 words
A double edge trigger flip-flop, comprising at least two inputs and at least three latches, wherein a first input and a second input are respectively coupled to a first tri-state inverter controlled by a clock control signal and a second tri-state inverter controlled by an inverted clock control signal, outputs of the first tri-state inverter and the second tri-state inverter are respectively coupled to a first latch and a second latch, outputs of the first latch and the second latch are respectively coupled to a third tri-state inverter controlled by the clock control signal and a fourth tri-state inverter controlled by the inverted clock control signal, outputs of the third tri-state inverter and the fourth tri-state inverter are respectively coupled to a first input and a second input of a third latch, wherein the third latch consists of two inverters, a first output and a second output of the third latch are respectively an output and inverted output of the double edge trigger flip-flop.

References Cited (Backward Citations)

US5281865A Cited
US5767716A Cited
US5867049A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-05-28 2004-11-27 2005-05-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2008-05-28 2008-11-27 2009-05-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2012-05-28 2012-11-27 2013-05-29 $7700.00 Window Closed / Lapsed

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