US5767716A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Noise insensitive high performance energy efficient push pull isolation flip-flop circuits
Assignee: Texas Instruments Inc
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Filing: 1996-09-25
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Granted: 1998-06-16
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Expires: 2016-09-25
Abstract
Abstract An energy efficient D flip-flop circuit has a master latch, a slave latch and a push-pull circuit. This push-pull circuit includes an inverter having an input connected to the output of the master latch and a transmission gate clocked in a second phase having an input connected to the output of the inverter and an output connected to the output of the slave latch. This push-pull circuit speeds the C-to-Q delay time of the circuit because there is only one gate delay to output using this circuit. The master and slave latches may employ N-type MOSFETS, CMOS transfer gates or tri-state inverters in the feedback path. The master latch may employ a double pass transistor logic input. The push-pull circuit may employ a tri-state invertor in place of the inverter and transmission gate.
Inventors
- 👤 Uming Ko
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 20:07
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K3/0375; H03K3/01; H03K3/012; H03K3/0372; H03K3/353; H03K3/356; H03K3/3562; H03K3/35625
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
303 words
A D flip-flop circuit having and input and an output comprising: a master latch having an input receiving an input signal of said D flip-flop circuit clocked in a first phase and an output, said master latch including a first master latch inverter having an input connected to said input of said master latch and an output serving as output of said master latch, a second master latch inverter having an input connected to said output of said first master latch inverter and an output, and an N-type MOSFET having a source-drain path connected between said output of said second master latch inverter and said input of said first master latch inverter and a base receiving a clock signal in a second phase opposite to said first phase; a slave latch having an input connected to said output of said master latch clocked in said second phase opposite to said first phase and an output serving as output of said D flip-flop circuit, said slave latch including a first slave latch inverter having an input connected to said input of said slave latch and an output serving as output of said slave latch, a second slave latch inverter having an input connected to said output of said first slave latch inverter and an output, and an N-type MOSFET having a source-drain path connected between said output of said second slave latch inverter and said input of said first slave latch inverter and a base receiving said clock signal in said first phase; and a push-pull circuit including an inverter having an input connected to said output of said master latch and an output, and a transmission gate clocked in said second phase having an input connected to said output of said inverter and an output connected to said output of said slave latch.
Claim 2
Dependent Claim
303 words
A D flip-flop circuit having and input and an output comprising: a master latch having an input receiving an input signal of said D flip-flop circuit clocked in a first phase and an output, said master latch including a first master latch inverter having an input connected to said input of said master latch and an output serving as output of said master latch, a second master latch inverter having an input connected to said output of said first master latch inverter and an output, and an N-type MOSFET having a source-drain path connected between said output of said second master latch inverter and said input of said first master latch inverter and a base receiving a clock signal in a second phase opposite to said first phase; a slave latch having an input connected to said output of said master latch clocked in said second phase opposite to said first phase and an output serving as output of said D flip-flop circuit, said slave latch including a first slave latch inverter having an input connected to said input of said slave latch and an output serving as output of said slave latch, a second slave latch inverter having an input connected to said output of said first slave latch inverter and an output, and an N-type MOSFET having a source-drain path connected between said output of said second slave latch inverter and said input of said first slave latch inverter and a base receiving said clock signal in said first phase; and a push-pull circuit including an inverter having an input connected to said output of said master latch and an output, and a transmission gate clocked in said second phase having an input connected to said output of said inverter and an output connected to said output of said slave latch.
Claim 3
Dependent Claim
33 words
The D flip-flop circuit of claim 1, wherein: said master latch includes a transmission gate clocked in said first phase having an input serving as input to said master latch and an output.
Claim 4
Dependent Claim
111 words
The D flip-flop circuit of claim 1, wherein: said master latch includes a double pass transistor logic input serving as input of said D flip-flop circuit clocked in said first phase and an output, said double pass transistor logic input including an N-type MOSFET having a source-drain path connected between said input of said D flip-flop circuit and a common terminal and a base receiving said clock signal in said first phase, and a P-type MOSFET having a source-drain path connected between said clock signal in said first phase and said common terminal and a base receiving an inverse of said input signal at said input of said D flip-flop circuit.
Claim 5
Dependent Claim
33 words
The D flip-flop circuit of claim 1, wherein: said slave latch including a transmission gate clocked in said second phase having an input serving as input to said slave latch and an output.
Claim 6
Dependent Claim
277 words
A D flip-flop circuit having and input and an output comprising: a master latch having an input receiving an input signal of said D flip-flop circuit clocked in a first phase and an output, said master latch including a first master latch inverter having an input connected to said input of said master latch and an output serving as output of said master latch, a second master latch inverter having an input connected to said output of said first master latch inverter and an output, and an N-type MOSFET having a source-drain path connected between said output of said second master latch inverter and said input of said first master latch inverter and a base receiving a clock signal in a second phase opposite to said first phase; a slave latch having an input connected to said output of said master latch clocked in said second phase opposite to said first phase and an output serving as output of said D flip-flop circuit, said slave latch including a first slave latch inverter having an input connected to said input of said slave latch and an output serving as output of said slave latch, a second slave latch inverter having an input connected to said output of said first slave latch inverter and an output, and an N-type MOSFET having a source-drain path connected between said output of said second slave latch inverter and said input of said first slave latch inverter and a base receiving said clock signal in said first phase; and a tri-state inverter having an input connected said output of said master latch and an output connected to said output of said slave latch.
Claim 7
Dependent Claim
277 words
A D flip-flop circuit having and input and an output comprising: a master latch having an input receiving an input signal of said D flip-flop circuit clocked in a first phase and an output, said master latch including a first master latch inverter having an input connected to said input of said master latch and an output serving as output of said master latch, a second master latch inverter having an input connected to said output of said first master latch inverter and an output, and an N-type MOSFET having a source-drain path connected between said output of said second master latch inverter and said input of said first master latch inverter and a base receiving a clock signal in a second phase opposite to said first phase; a slave latch having an input connected to said output of said master latch clocked in said second phase opposite to said first phase and an output serving as output of said D flip-flop circuit, said slave latch including a first slave latch inverter having an input connected to said input of said slave latch and an output serving as output of said slave latch, a second slave latch inverter having an input connected to said output of said first slave latch inverter and an output, and an N-type MOSFET having a source-drain path connected between said output of said second slave latch inverter and said input of said first slave latch inverter and a base receiving said clock signal in said first phase; and a tri-state inverter having an input connected said output of said master latch and an output connected to said output of said slave latch.
Claim 8
Dependent Claim
138 words
The D flip-flop circuit of claim 5, wherein: said tri-state inverter includes a first P-type MOSFET having a source-drain path connected between a supply voltage and a first common terminal and a base connected to said output of said master latch, a second P-type MOSFET having a source-drain path connected between said first common terminal and said output of said slave latch and a base receiving said clock signal in said first phase, a first N-type MOSFET having a source-drain path connected between said output of said slave latch and a second common terminal and a base receiving said clock signal in said second phase inverse to said first phase, and a second N-type MOSFET having a source-drain path connected between said second common terminal and ground and a base connected to said output of said master latch.
Claim 9
Dependent Claim
33 words
The D flip-flop circuit of claim 5, wherein: said master latch includes a transmission gate clocked in said first phase having an input serving as input to said master latch and an output.
Claim 10
Dependent Claim
111 words
The D flip-flop circuit of claim 5, wherein: said master latch includes a double pass transistor logic input serving as input of said D flip-flop circuit clocked in said first phase and an output, said double pass transistor logic input including an N-type MOSFET having a source-drain path connected between said input of said D flip-flop circuit and a common terminal and a base receiving said clock signal in said first phase, and a P-type MOSFET having a source-drain path connected between said clock signal in said first phase and said common terminal and a base receiving an inverse of said input signal at said input of said D flip-flop circuit.
Claim 11
Dependent Claim
33 words
The D flip-flop circuit of claim 5, wherein: said slave latch includes a transmission gate clocked in said second phase having an input serving as input to said slave latch and an output.
Claim 12
Dependent Claim
297 words
A D flip-flop circuit having and input and an output comprising: a master latch having an input receiving an input signal of said D flip-flop circuit clocked in a first phase and an output, said master latch including a first master latch inverter having an input connected to said input of said master latch and an output serving as output of said master latch, a second master latch inverter having an input connected to said output of said first master latch inverter and an output, and a transmission gate clocked in a second phase opposite to said first phase having an input connected to said output of said second master latch inverter and an output connected to said input of said first master latch inverter; a slave latch having an input connected to said output of said master latch clocked in said second phase opposite to said first phase and an output serving as output of said D flip-flop circuit, said slave latch including a first slave latch inverter having an input connected to said input of said slave latch and an output serving as output of said slave latch, a second slave latch inverter having an input connected to said output of said first slave latch inverter and an output, and a transmission gate clocked in said first phase having an input connected to said output of said second slave latch inverter and an output connected to said input of said first slave latch inverter; and a push-pull circuit including an inverter having an input connected to said output of said master latch and an output, and a transmission gate clocked in said second phase having an input connected to said output of said inverter and an output connected to said output of said slave latch.
Claim 13
Dependent Claim
297 words
A D flip-flop circuit having and input and an output comprising: a master latch having an input receiving an input signal of said D flip-flop circuit clocked in a first phase and an output, said master latch including a first master latch inverter having an input connected to said input of said master latch and an output serving as output of said master latch, a second master latch inverter having an input connected to said output of said first master latch inverter and an output, and a transmission gate clocked in a second phase opposite to said first phase having an input connected to said output of said second master latch inverter and an output connected to said input of said first master latch inverter; a slave latch having an input connected to said output of said master latch clocked in said second phase opposite to said first phase and an output serving as output of said D flip-flop circuit, said slave latch including a first slave latch inverter having an input connected to said input of said slave latch and an output serving as output of said slave latch, a second slave latch inverter having an input connected to said output of said first slave latch inverter and an output, and a transmission gate clocked in said first phase having an input connected to said output of said second slave latch inverter and an output connected to said input of said first slave latch inverter; and a push-pull circuit including an inverter having an input connected to said output of said master latch and an output, and a transmission gate clocked in said second phase having an input connected to said output of said inverter and an output connected to said output of said slave latch.
Claim 14
Dependent Claim
33 words
The D flip-flop circuit of claim 10, wherein: said master latch includes a transmission gate clocked in said first phase having an input serving as input to said master latch and an output.
Claim 15
Dependent Claim
111 words
The D flip-flop circuit of claim 10, wherein: said master latch includes a double pass transistor logic input serving as input of said D flip-flop circuit clocked in said first phase and an output, said double pass transistor logic input including an N-type MOSFET having a source-drain path connected between said input of said D flip-flop circuit and a common terminal and a base receiving said clock signal in said first phase, and a P-type MOSFET having a source-drain path connected between said clock signal in said first phase and said common terminal and a base receiving an inverse of said input signal at said input of said D flip-flop circuit.
Claim 16
Dependent Claim
33 words
The D flip-flop circuit of claim 10, wherein: said slave latch including a transmission gate clocked in said second phase having an input serving as input to said slave latch and an output.
Claim 17
Dependent Claim
297 words
A D flip-flop circuit having and input and an output comprising: a master latch having an input receiving an input signal of said D flip-flop circuit clocked in a first phase and an output, said master latch including a first master latch inverter having an input connected to said input of said master latch and an output serving as output of said master latch, a second master latch inverter having an input connected to said output of said first master latch inverter and an output, and a master transmission gate clocked in a second phase opposite to said first phase having an input connected to said output of said second master latch inverter and an output connected to said input of said first master latch inverter; a slave latch having an input connected to said output of said master latch clocked in said second phase opposite to said first phase and an output serving as output of said D flip-flop circuit, said slave latch including a first slave transmission gate clocked in said second phase having an input serving as input to said slave latch and an output, a first slave latch inverter having an input connected to said output of said transmission gate and an output serving as output of said slave latch, a second slave latch inverter having an input connected to said output of said first slave latch inverter and an output, and a second slave transmission gate clocked in said first phase having an input connected to said output of said second slave latch inverter and an output connected to said input of said first slave latch inverter; and a tri-state inverter having an input connected said output of said master latch and an output connected to said output of said slave latch.
Claim 18
Dependent Claim
297 words
A D flip-flop circuit having and input and an output comprising: a master latch having an input receiving an input signal of said D flip-flop circuit clocked in a first phase and an output, said master latch including a first master latch inverter having an input connected to said input of said master latch and an output serving as output of said master latch, a second master latch inverter having an input connected to said output of said first master latch inverter and an output, and a master transmission gate clocked in a second phase opposite to said first phase having an input connected to said output of said second master latch inverter and an output connected to said input of said first master latch inverter; a slave latch having an input connected to said output of said master latch clocked in said second phase opposite to said first phase and an output serving as output of said D flip-flop circuit, said slave latch including a first slave transmission gate clocked in said second phase having an input serving as input to said slave latch and an output, a first slave latch inverter having an input connected to said output of said transmission gate and an output serving as output of said slave latch, a second slave latch inverter having an input connected to said output of said first slave latch inverter and an output, and a second slave transmission gate clocked in said first phase having an input connected to said output of said second slave latch inverter and an output connected to said input of said first slave latch inverter; and a tri-state inverter having an input connected said output of said master latch and an output connected to said output of said slave latch.
Claim 19
Dependent Claim
138 words
The D flip-flop circuit of claim 14, wherein: said tri-state inverter includes a first P-type MOSFET having a source-drain path connected between a supply voltage and a first common terminal and a base connected to said output of said master latch, a second P-type MOSFET having a source-drain path connected between said first common terminal and said output of said slave latch and a base receiving a clock signal in said first phase, a first N-type MOSFET having a source-drain path connected between said output of said slave latch and a second common terminal and a base receiving said clock signal in said second phase inverse to said first phase, and a second N-type MOSFET having a source-drain path connected between said second common terminal and ground and a base connected to said output of said master latch.
Claim 20
Dependent Claim
33 words
The D flip-flop circuit of claim 14, wherein: said master latch includes a transmission gate clocked in said first phase having an input serving as input to said master latch and an output.
Claim 21
Dependent Claim
111 words
The D flip-flop circuit of claim 14, wherein: said master latch includes a double pass transistor logic input serving as input of said D flip-flop circuit clocked in said first phase and an output, said double pass transistor logic input including an N-type MOSFET having a source-drain path connected between said input of said D flip-flop circuit and a common terminal and a base receiving a clock signal in said first phase, and a P-type MOSFET having a source-drain path connected between said clock signal in said first phase and said common terminal and a base receiving an inverse of said input signal at said input of said D flip-flop circuit.
Claim 22
Dependent Claim
238 words
A D flip-flop circuit having and input and an output comprising: a master latch having an input receiving an input signal of said D flip-flop circuit clocked in a first phase and an output, said master latch including a first master latch inverter having an input connected to said input of said master latch and an output serving as output of said master latch, a master tri-state inverter having an input connected said output of said first master latch inverter and an output connected to said input of said first master latch inverter; a slave latch having an input connected to said output of said master latch clocked in said second phase opposite to said first phase and an output serving as output of said D flip-flop circuit, said slave latch including a first slave latch inverter having an input connected to said input of said slave latch and an output serving as output of said slave latch, a slave tri-state inverter having an input connected said output of said first slave latch inverter and an output connected to said input of said first slave latch inverter; and a push-pull circuit including an inverter having an input connected to said output of said master latch and an output, and a transmission gate clocked in said second phase having an input connected to said output of said inverter and an output connected to said output of said slave latch.
Claim 23
Dependent Claim
238 words
A D flip-flop circuit having and input and an output comprising: a master latch having an input receiving an input signal of said D flip-flop circuit clocked in a first phase and an output, said master latch including a first master latch inverter having an input connected to said input of said master latch and an output serving as output of said master latch, a master tri-state inverter having an input connected said output of said first master latch inverter and an output connected to said input of said first master latch inverter; a slave latch having an input connected to said output of said master latch clocked in said second phase opposite to said first phase and an output serving as output of said D flip-flop circuit, said slave latch including a first slave latch inverter having an input connected to said input of said slave latch and an output serving as output of said slave latch, a slave tri-state inverter having an input connected said output of said first slave latch inverter and an output connected to said input of said first slave latch inverter; and a push-pull circuit including an inverter having an input connected to said output of said master latch and an output, and a transmission gate clocked in said second phase having an input connected to said output of said inverter and an output connected to said output of said slave latch.
Claim 24
Dependent Claim
139 words
The D flip-flop circuit of claim 18, wherein: said master tri-state inverter includes a first P-type MOSFET having a source-drain path connected between a supply voltage and a first common terminal and a base connected to said output of said master latch, a second P-type MOSFET having a source-drain path connected between said first common terminal and said input of said master latch and a base receiving a clock signal in said first phase, a first N-type MOSFET having a source-drain path connected between said input of said master latch and a second common terminal and a base receiving said clock signal in said second phase inverse to said first phase, and a second N-type MOSFET having a source-drain path connected between said second common terminal and ground and a base connected to said output of said master latch.
Claim 25
Dependent Claim
139 words
The D flip-flop circuit of claim 18, wherein: said slave tri-state inverter includes a first P-type MOSFET having a source-drain path connected between a supply voltage and a first common terminal and a base connected to said output of said slave latch, a second P-type MOSFET having a source-drain path connected between said first common terminal and said input of said slave latch and a base receiving a clock signal in said first phase, a first N-type MOSFET having a source-drain path connected between said input of said slave latch and a second common terminal and a base receiving said clock signal in said second phase inverse to said first phase, and a second N-type MOSFET having a source-drain path connected between said second common terminal and ground and a base connected to said output of said slave latch.
Claim 26
Dependent Claim
33 words
The D flip-flop circuit of claim 18, wherein: said master latch includes a transmission gate clocked in said first phase having an input serving as input to said master latch and an output.
Claim 27
Dependent Claim
111 words
The D flip-flop circuit of claim 18, wherein: said master latch includes a double pass transistor logic input serving as input of said D flip-flop circuit clocked in said first phase and an output, said double pass transistor logic input including an N-type MOSFET having a source-drain path connected between said input of said D flip-flop circuit and a common terminal and a base receiving a clock signal in said first phase, and a P-type MOSFET having a source-drain path connected between said clock signal in said first phase and said common terminal and a base receiving an inverse of said input signal at said input of said D flip-flop circuit.
Claim 28
Dependent Claim
33 words
The D flip-flop circuit of claim 18, wherein: said slave latch including a transmission gate clocked in said second phase having an input serving as input to said slave latch and an output.
Claim 29
Dependent Claim
213 words
A D flip-flop circuit having and input and an output comprising: a master latch having an input receiving an input signal of said D flip-flop circuit clocked in a first phase and an output, said master latch including a first master latch inverter having an input connected to said input of said master latch and an output serving as output of said master latch, a master tri-state inverter having an input connected said output of said first master latch inverter and an output connected to said input of said first master latch inverter; a slave latch having an input connected to said output of said master latch clocked in said second phase opposite to said first phase and an output serving as output of said D flip-flop circuit, said slave latch including a first slave latch inverter having an input connected to said input of said slave latch and an output serving as output of said slave latch, a slave tri-state inverter having an input connected said output of said first slave latch inverter and an output connected to said input of said first slave latch inverter; and a push-pull tri-state inverter having an input connected said output of said master latch and an output connected to said output of said slave latch.
Claim 30
Dependent Claim
213 words
A D flip-flop circuit having and input and an output comprising: a master latch having an input receiving an input signal of said D flip-flop circuit clocked in a first phase and an output, said master latch including a first master latch inverter having an input connected to said input of said master latch and an output serving as output of said master latch, a master tri-state inverter having an input connected said output of said first master latch inverter and an output connected to said input of said first master latch inverter; a slave latch having an input connected to said output of said master latch clocked in said second phase opposite to said first phase and an output serving as output of said D flip-flop circuit, said slave latch including a first slave latch inverter having an input connected to said input of said slave latch and an output serving as output of said slave latch, a slave tri-state inverter having an input connected said output of said first slave latch inverter and an output connected to said input of said first slave latch inverter; and a push-pull tri-state inverter having an input connected said output of said master latch and an output connected to said output of said slave latch.
Claim 31
Dependent Claim
139 words
The D flip-flop circuit of claim 24, wherein: said push-pull tri-state inverter includes a first P-type MOSFET having a source-drain path connected between a supply voltage and a first common terminal and a base connected to said output of said master latch, a second P-type MOSFET having a source-drain path connected between said first common terminal and said output of said slave latch and a base receiving a clock signal in said first phase, a first N-type MOSFET having a source-drain path connected between said output of said slave latch and a second common terminal and a base receiving said clock signal in said second phase inverse to said first phase, and a second N-type MOSFET having a source-drain path connected between said second common terminal and ground and a base connected to said output of said master latch.
Claim 32
Dependent Claim
139 words
The D flip-flop circuit of claim 24, wherein: said master tri-state inverter includes a first P-type MOSFET having a source-drain path connected between a supply voltage and a first common terminal and a base connected to said output of said master latch, a second P-type MOSFET having a source-drain path connected between said first common terminal and said input of said master latch and a base receiving a clock signal in said first phase, a first N-type MOSFET having a source-drain path connected between said input of said master latch and a second common terminal and a base receiving said clock signal in said second phase inverse to said first phase, and a second N-type MOSFET having a source-drain path connected between said second common terminal and ground and a base connected to said output of said master latch.
Claim 33
Dependent Claim
139 words
The D flip-flop circuit of claim 24, wherein: said slave tri-state inverter includes a first P-type MOSFET having a source-drain path connected between a supply voltage and a first common terminal and a base connected to said output of said slave latch, a second P-type MOSFET having a source-drain path connected between said first common terminal and said input of said slave latch and a base receiving a clock signal in said first phase, a first N-type MOSFET having a source-drain path connected between said input of said slave latch and a second common terminal and a base receiving said clock signal in said second phase inverse to said first phase, and a second N-type MOSFET having a source-drain path connected between said second common terminal and ground and a base connected to said output of said slave latch.
Claim 34
Dependent Claim
33 words
The D flip-flop circuit of claim 24, wherein: said master latch includes a transmission gate clocked in said first phase having an input serving as input to said master latch and an output.
Claim 35
Dependent Claim
111 words
The D flip-flop circuit of claim 24, wherein: said master latch includes a double pass transistor logic input serving as input of said D flip-flop circuit clocked in said first phase and an output, said double pass transistor logic input including an N-type MOSFET having a source-drain path connected between said input of said D flip-flop circuit and a common terminal and a base receiving a clock signal in said first phase, and a P-type MOSFET having a source-drain path connected between said clock signal in said first phase and said common terminal and a base receiving an inverse of said input signal at said input of said D flip-flop circuit.
Claim 36
Dependent Claim
33 words
The D flip-flop circuit of claim 24, wherein: said slave latch includes a transmission gate clocked in said second phase having an input serving as input to said slave latch and an output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-15 | 2001-12-15 | 2002-06-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-15 | 2005-12-15 | 2006-06-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-15 | 2009-12-15 | 2010-06-16 | $7700.00 | Window Closed / Lapsed |