Patent US6239631B1 successfully refreshed from Google Patents.
US6239631B1
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Integrated circuit device with input buffer capable of correspondence with highspeed clock
Assignee: Socionext Inc
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Filing: 1999-08-19
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Granted: 2001-05-29
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Expires: 2019-08-19
Abstract
Abstract One aspect of the present invention is characterized in that an input buffer circuit constitutes either 2 sets, or a plurality of sets relative to 1 input signal, either a pair of complementary internal clocks, or a plurality of internal clocks are generated by frequency-dividing a supplied clock inside the integrated circuit device, and input signals are received and latched either in synchronization with a pair of complementary clocks, or in synchronization with a plurality of clocks in accordance with an input buffer of either 2 sets or a plurality of sets. The output of input buffers of either 2 sets or a plurality of sets are combined by a combining circuit, and supplied internally. An H level or an L level period is set for the internally-generated internal clock so that outputs from the various input buffers are not in contention with one another. According to the present invention, the operation of input buffers of a plurality of sets are synchronized with internal clocks of a slower speed than a supplied clock, thus enabling the reliable receive of input signals.
Inventors
- 👤 Shinya Fujioka
- 👤 Hiroyoshi Tomita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:17
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/00; G11C7/10; G11C7/1078; G11C7/1093; G06; G06F; G06F5/00; G06F5/06; G11C7/1087; G11C7/22; G11C7/222; H; H03; H03L; H03L7/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
137 words
An integrated circuit device, which has an input buffer that receives and latches an input signal in synchronization with a supplied clock, comprising: a frequency-dividing circuit for generating a plurality of different-phase internal clocks by frequency-dividing said supplied clock; a plurality of input buffers, each receiving and latching said input signal in synchronization with corresponding one of said plurality of internal clocks; and a combining circuit for combining the outputs of said plurality of input buffers, wherein: said combining circuit comprises: a plurality of tri-state buffers, which constitute either a low impedance state of either an H level or an L level or a high impedance state in response to the respective outputs of said plurality of input buffers; and a common output latching circuit, to which the outputs of said plurality of tri-state buffers are supplied.
Claim 2
Dependent Claim
137 words
An integrated circuit device, which has an input buffer that receives and latches an input signal in synchronization with a supplied clock, comprising: a frequency-dividing circuit for generating a plurality of different-phase internal clocks by frequency-dividing said supplied clock; a plurality of input buffers, each receiving and latching said input signal in synchronization with corresponding one of said plurality of internal clocks; and a combining circuit for combining the outputs of said plurality of input buffers, wherein: said combining circuit comprises: a plurality of tri-state buffers, which constitute either a low impedance state of either an H level or an L level or a high impedance state in response to the respective outputs of said plurality of input buffers; and a common output latching circuit, to which the outputs of said plurality of tri-state buffers are supplied.
Claim 3
Dependent Claim
147 words
An integrated circuit device, which has an input buffer that receives and latches an input signal in synchronization with a supplied clock, comprising: a frequency-dividing circuit for generating a plurality of different-phase internal clocks by frequency-dividing said supplied clock; a plurality of input buffers, each receiving and latching said input signal in synchronization with corresponding one of said plurality of internal clocks; a combining circuit for combining the outputs of said plurality of input buffers; a mode register, in which a frequency division control signal is set in accordance with the frequency of said supplied clock; and said frequency-dividing circuit, in accordance with said frequency division control signal, performs a frequency division operation when the frequency of said supplied clock is higher than a predetermined frequency, and does not perform a frequency division operation when the frequency of said supplied clock is lower than said predetermined frequency.
Claim 4
Dependent Claim
147 words
An integrated circuit device, which has an input buffer that receives and latches an input signal in synchronization with a supplied clock, comprising: a frequency-dividing circuit for generating a plurality of different-phase internal clocks by frequency-dividing said supplied clock; a plurality of input buffers, each receiving and latching said input signal in synchronization with corresponding one of said plurality of internal clocks; a combining circuit for combining the outputs of said plurality of input buffers; a mode register, in which a frequency division control signal is set in accordance with the frequency of said supplied clock; and said frequency-dividing circuit, in accordance with said frequency division control signal, performs a frequency division operation when the frequency of said supplied clock is higher than a predetermined frequency, and does not perform a frequency division operation when the frequency of said supplied clock is lower than said predetermined frequency.
Claim 5
Dependent Claim
129 words
An integrated circuit device, which has an input buffer that receives and latches an input signal in synchronization with a supplied clock, comprising: a frequency-dividing circuit for generating a plurality of different-phase internal clocks by frequency-dividing said supplied clock; a plurality of input buffers, each receiving and latching said input signal in synchronization with corresponding one of said plurality of internal clocks; a combining circuit for combining the outputs of said plurality of input buffers; a frequency division control setting element, in which a frequency division control signal is set; and said frequency-dividing circuit performs said frequency division operation when said frequency division control signal is in a first state, and does not perform said frequency division operation when said frequency division control signal is in a second state.
Claim 6
Dependent Claim
129 words
An integrated circuit device, which has an input buffer that receives and latches an input signal in synchronization with a supplied clock, comprising: a frequency-dividing circuit for generating a plurality of different-phase internal clocks by frequency-dividing said supplied clock; a plurality of input buffers, each receiving and latching said input signal in synchronization with corresponding one of said plurality of internal clocks; a combining circuit for combining the outputs of said plurality of input buffers; a frequency division control setting element, in which a frequency division control signal is set; and said frequency-dividing circuit performs said frequency division operation when said frequency division control signal is in a first state, and does not perform said frequency division operation when said frequency division control signal is in a second state.
Claim 7
Dependent Claim
42 words
The integrated circuit device according to claim 2 wherein: when said frequency-dividing circuit does not perform a frequency division operation, a prescribed input buffer among said plurality of input buffers receives and latches said input signal in synchronization with said supplied clock.
Claim 8
Dependent Claim
117 words
An integrated circuit device, which has an input buffer that receives and latches an input signal in synchronization with a supplied clock, comprising: a frequency-dividing circuit for generating a plurality of different-phase internal clocks by frequency-dividing said supplied clock; a plurality of input buffers, each receiving and latching said input signal in synchronization with corresponding one of said plurality of internal clocks; a combining circuit for combining the outputs of said plurality of input buffers; an internal clock inputting circuit, which, when said one level of said frequency-divided internal clocks overlaps, changes the leading internal clock to the other level; and said plurality of input buffers input respective said internal clocks via said internal clock inputting circuit.
Claim 9
Dependent Claim
117 words
An integrated circuit device, which has an input buffer that receives and latches an input signal in synchronization with a supplied clock, comprising: a frequency-dividing circuit for generating a plurality of different-phase internal clocks by frequency-dividing said supplied clock; a plurality of input buffers, each receiving and latching said input signal in synchronization with corresponding one of said plurality of internal clocks; a combining circuit for combining the outputs of said plurality of input buffers; an internal clock inputting circuit, which, when said one level of said frequency-divided internal clocks overlaps, changes the leading internal clock to the other level; and said plurality of input buffers input respective said internal clocks via said internal clock inputting circuit.
Claim 10
Dependent Claim
124 words
An integrated circuit device, which has an input buffer that receives and latches an input signal in synchronization with a supplied clock, comprising: a frequency-dividing circuit for generating a plurality of different-phase internal clocks by frequency-dividing said supplied clock; a plurality of input buffers, each receiving and latching said input signal in synchronization with corresponding one of said plurality of internal clocks; a combining circuit for combining the outputs of said plurality of input buffers; a clock compensating circuit for adjusting the phases of said internal clocks, generated by said frequency-dividing circuit, to a prescribed relationship with the phase of said supplied clock; wherein said internal clocks, the phases of which are adjusted by said clock compensating circuit, are supplied to said input buffers.
Claim 11
Dependent Claim
124 words
An integrated circuit device, which has an input buffer that receives and latches an input signal in synchronization with a supplied clock, comprising: a frequency-dividing circuit for generating a plurality of different-phase internal clocks by frequency-dividing said supplied clock; a plurality of input buffers, each receiving and latching said input signal in synchronization with corresponding one of said plurality of internal clocks; a combining circuit for combining the outputs of said plurality of input buffers; a clock compensating circuit for adjusting the phases of said internal clocks, generated by said frequency-dividing circuit, to a prescribed relationship with the phase of said supplied clock; wherein said internal clocks, the phases of which are adjusted by said clock compensating circuit, are supplied to said input buffers.
Claim 12
Dependent Claim
43 words
The integrated circuit device according to claim 3 , wherein: when said frequency-dividing circuit does not perform a frequency division operation, a prescribed input buffer among said plurality of input buffers receives and latches said input signal in synchronization with said supplied clock.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-05-28 | 2004-11-27 | 2005-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-05-28 | 2008-11-27 | 2009-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-05-28 | 2012-11-27 | 2013-05-29 | $7700.00 | Window Closed / Lapsed |