Interface circuit with high speed data transmission

Claim 2

An interface circuit comprising: a clock signal generator outputting a clock signal and an inversion clock signal; a shift signal generator receiving a start signal, the clock signal and the inversion clock signal, and outputting shift signals having odd shift signals and even shift signals, the odd shift signals including a first odd shift signal and subsequent odd shift signals, wherein the first odd shift signal is generated in response to the start signal and the clock signal, wherein the even shift signals are generated in response to a previous one of the odd shift signals and the inversion clock signal, and wherein the subsequent odd shift signals are generated in response to a previous one of the even shift signals and the clock signal; a data distribution circuit receiving data, the clock signal and the inversion clock signal, said data distribution circuit outputting odd data in response to the data and the clock signal, and outputting even data in response to the data and the inversion clock signal; a plurality of odd data output circuits each of which receives the odd data and outputs the received data in response to one of the odd shift signals, respectively; and a plurality of even data output circuits each of which receives the even data and outputs the received data in response to one of the even shift signals, respectively.

Claim 3

An interface circuit according to claim 1, wherein said clock signal generator is a frequency divider receiving an original clock signal and outputting a frequency divided signal and an inversion signal thereof as the clock signal and the inversion clock signal.

Claim 4

An interface circuit according to claim 2, wherein said frequency divider is a flip flop circuit including a clock terminal receiving the original clock signal, an output terminal outputting the clock signal, an inverse output terminal outputting the inversion clock signal and an input terminal connected to the inverse output terminal thereof.

Claim 5

An interface circuit according to claim 1, wherein said clock signal generator includes a clock source and an inverter.

Claim 6

An interface circuit according to claim 1, wherein said shift signal generator is a shift register having a plurality of cascade connected flip flop circuits including a first flip flop circuit having a clock terminal receiving the clock signal, an input terminal receiving the start signal and an output terminal outputting the first odd shift signal, even flip flop circuits each having an enable terminal receiving the inversion clock signal, an input terminal receiving a previous one of the odd shift signals and an output terminal outputting one of the even shift signals, and odd flip flop circuits each having an enable terminal receiving the clock signal, an input terminal receiving a previous one of the even shift signals and an output terminal outputting one of the subsequent odd shift signals.

Claim 7

An interface circuit according to claim 1, wherein said data distribution circuit includes a first flip flop circuit having an input terminal receiving the data, an output terminal outputting the odd data and a clock terminal receiving the clock signal and a second flip flop circuit having an input terminal receiving the data, an output terminal outputting the even data and a clock terminal receiving the inversion clock signal.

Claim 8

An interface circuit according to claim 1, wherein each of said odd data output circuits is a flip flop circuit having an input terminal receiving the odd data, an enable terminal receiving one of the odd shift signals and an output terminal outputting the received data.

Claim 9

An interface circuit according to claim 1, wherein each of said even data output circuits is a flip flop circuit having an input terminal receiving the even data, an enable terminal receiving one of the even shift signals and an output terminal outputting the received data.

Claim 10

An interface circuit comprising: a clock signal generator outputting a first clock signal having a frequency and a second clock signal having the same frequency of the first clock signal and a predetermined delay with the first clock signal; a shift signal generator receiving a start signal and the first and second clock signals, and outputting shift signals having first shift signals and second shift signals, the first shift signals including a top first shift signal and subsequent first shift signals, wherein the top first shift signal is generated in response to the start signal and the first clock signal, wherein the second shift signals are generated in response to a previous one of the first shift signals and the inversion clock signal, and wherein the subsequent first shift signals are generated in response to a previous one of the second shift signals and the clock signal; a data distribution circuit receiving data and the first and second clock signals, said data distribution circuit outputting first data in response to the data and the first clock signal, and outputting second data in response to the data and the second clock signal; a plurality of first data output circuits each of which receives the first data and outputs the received first data in response to one of the first shift signals, respectively; and a plurality of second data output circuits each of which receives the second data and outputs the received second data in response to one of the second shift signals, respectively.

Claim 11

An interface circuit comprising: a clock signal generator outputting a first clock signal having a frequency and a second clock signal having the same frequency of the first clock signal and a predetermined delay with the first clock signal; a shift signal generator receiving a start signal and the first and second clock signals, and outputting shift signals having first shift signals and second shift signals, the first shift signals including a top first shift signal and subsequent first shift signals, wherein the top first shift signal is generated in response to the start signal and the first clock signal, wherein the second shift signals are generated in response to a previous one of the first shift signals and the inversion clock signal, and wherein the subsequent first shift signals are generated in response to a previous one of the second shift signals and the clock signal; a data distribution circuit receiving data and the first and second clock signals, said data distribution circuit outputting first data in response to the data and the first clock signal, and outputting second data in response to the data and the second clock signal; a plurality of first data output circuits each of which receives the first data and outputs the received first data in response to one of the first shift signals, respectively; and a plurality of second data output circuits each of which receives the second data and outputs the received second data in response to one of the second shift signals, respectively.

Claim 12

An interference circuit according to claim 9, wherein said clock signal generator is a frequency divider receiving an original clock signal and outputting a frequency divided signal and an inversion signal thereof as the first and second clock signals.

Claim 13

An interface circuit according to claim 10, wherein said frequency divider is a flip flop circuit including a clock terminal receiving the original clock signal, an output terminal outputting the first clock signal, an inverse output terminal outputting the second clock signal and an input terminal connected to the inverse output terminal thereof.

Claim 14

An interface circuit according to claim 9, wherein said clock signal generator includes a clock source and an inverter.

Claim 15

An interface circuit according to claim 9, wherein said shift signal generator is a shift register having a plurality of cascade connected flip flop circuits including a top flip flop circuit having a clock terminal receiving the first clock signal, an input terminal receiving the start signal and an output terminal outputting the top first shift signal, first flip flop circuits each having an enable terminal receiving the second clock signal, an input terminal connected to the output terminal of a previous one of the first shift signals and an output terminal outputting one of the second shift signals, and second flip flop circuits each having an enable terminal receiving the first clock signal, input terminal connected to the output terminal of a previous one of the second shift signals and output terminal outputting one of the subsequent first shift signals.

Claim 16

An interface circuit according to claim 9, wherein said data distribution circuit includes a first flip flop circuit having an input terminal receiving the data, an output terminal outputting the first data and a clock terminal receiving the first clock signal and a second flip flop circuit having an input terminal receiving the data, an output terminal outputting the second data and a clock terminal receiving the second clock signal.

Claim 17

An interface circuit according to claim 9, wherein each of said first data output circuits is a flip flop circuit having an input terminal receiving the first data, an enable terminal receiving one of the first shift signals and an output terminal outputting the received data.

Claim 18

An interface circuit according to claim 9, wherein each of said second data output circuits is a flip flop circuit having an input terminal receiving the second data, an enable terminal receiving one of the second shift signals and an output terminal outputting the received data.

Claim 19

An interface circuit comprising: a clock signal phase shifter outputting a plurality of clock signals each having the same frequency and a predetermined phase shift; a shift signal generator receiving a start signal and the clock signals and outputting shift signals, wherein a top shift signal of the shift signals is generated in response to the start signal and one of the clock signals, and wherein each of the other shift signals generated in response to a previous one of the shift signals and a one of the clock signals having the predetermined phase shift from another one of the clock signals that the previous one of the shift signals was generated in response to; a data distribution circuit receiving data and the clock signals, said data distribution circuit outputting shift data in response to the data and one of the clock signals so that the shift data are distributed depending on the predetermined phase shift value of one of the clock signals; a plurality of data output circuits each of which receives the shift data distributed by the data distribution circuit and outputs the received shift data in response to one of the shift signals, respectively.

Claim 20

An interface circuit comprising: a clock signal phase shifter outputting a plurality of clock signals each having the same frequency and a predetermined phase shift; a shift signal generator receiving a start signal and the clock signals and outputting shift signals, wherein a top shift signal of the shift signals is generated in response to the start signal and one of the clock signals, and wherein each of the other shift signals generated in response to a previous one of the shift signals and a one of the clock signals having the predetermined phase shift from another one of the clock signals that the previous one of the shift signals was generated in response to; a data distribution circuit receiving data and the clock signals, said data distribution circuit outputting shift data in response to the data and one of the clock signals so that the shift data are distributed depending on the predetermined phase shift value of one of the clock signals; a plurality of data output circuits each of which receives the shift data distributed by the data distribution circuit and outputs the received shift data in response to one of the shift signals, respectively.

Claim 21

An interface circuit according to claim 17, wherein the predetermined phase shift is 180 degrees.

Claim 22

An interface circuit according to claim 17, wherein the predetermined phase shift is 90 degrees.

Claim 23

An interface circuit according to claim 17, wherein the predetermined phase shift is 120 degrees.