US5999023A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock forwarding circuit in semiconductor integrated circuit and clock forwarding method
Assignee: Samsung Electronics Co Ltd
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Filing: 1998-05-14
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Granted: 1999-12-07
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Expires: 2018-05-14
Abstract
Abstract A clock forwarding circuit of a semiconductor integrated circuit which increases an operation timing margin of a data receive port and reduces power consumption, and a clock forwarding method, are provided. In the clock forwarding circuit for performing the clock forwarding method, upon abnormal operation of the semiconductor integrated circuit, such as during power-up or initialization, the data receive port captures the amount of interconnection delay of a data line and generates a receive clock signal which is self-generated, from a delayed send clock transmitted from a data send port via the data line. On the other hand, when the circuit operates in a normal operation mode, the data receive port receives data transmitted from the data send port via the data line, in response to the self-generated receive clock. Accordingly, the amount of interconnection delay of the data line is previously captured and data is received in response to the self-generated receive clock. Thus, the operation timing margin of the data receive port is increased. Also, a separate clock line is not required, and the send clock is supplied to the data receive port via the data line only upon abnormal operation of the semiconductor integrated circuit, so that power consumption is reduced.
Inventors
- 👤 Seok jin Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 23:02
CPC Classifications
H; H03; H03K; H03K3/00; H03L; H03L7/00; H03K5/00; H03K5/13; H03K5/135; H04; H04L; H04L7/00; H04L7/0008; H04L7/0012
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
119 words
A clock forwarding circuit of a semiconductor integrated circuit, comprising: a data sending latch for latching data in response to a send clock; a selector for selecting either the send clock or the output of the data sending latch, in response to a control signal; a data line for transmitting the output of the selector; a distributor for distributing delayed data and a delayed send clock transmitted via the data line, in response to the control signal; a clock generator for receiving a target clock and the delayed send clock output by the distributor and generating a receive clock; and a data receiving latch for latching the delayed data output by the distributor in response to the receive clock.
Claim 2
Dependent Claim
119 words
A clock forwarding circuit of a semiconductor integrated circuit, comprising: a data sending latch for latching data in response to a send clock; a selector for selecting either the send clock or the output of the data sending latch, in response to a control signal; a data line for transmitting the output of the selector; a distributor for distributing delayed data and a delayed send clock transmitted via the data line, in response to the control signal; a clock generator for receiving a target clock and the delayed send clock output by the distributor and generating a receive clock; and a data receiving latch for latching the delayed data output by the distributor in response to the receive clock.
Claim 3
Dependent Claim
33 words
The clock forwarding circuit as claimed in claim 1, further comprising a driver connected between the selector and the data line, for receiving the output of the selector and driving the data line.
Claim 4
Dependent Claim
30 words
The clock forwarding circuit as claimed in claim 1, further comprising another data receiving latch for latching the output of the data receiving latch in response to the target clock.
Claim 5
Dependent Claim
23 words
The clock forwarding circuit as claimed in claim 1, wherein the control signal indicates abnormal or normal operation of the semiconductor integrated circuit.
Claim 6
Dependent Claim
53 words
The clock forwarding circuit as claimed in claim 1, wherein: the selector selects and outputs the output of the data sending latch when the semiconductor integrated circuit operates in a normal operational mode; and the selector selects and outputs the send clock when the semiconductor integrated circuit operates in an abnormal operational mode.
Claim 7
Dependent Claim
18 words
The clock forwarding circuit as claimed in claim 5, wherein the abnormal operation mode is a power-up mode.
Claim 8
Dependent Claim
18 words
The clock forwarding circuit as claimed in claim 5, wherein the abnormal operational mode is an initialization mode.
Claim 9
Dependent Claim
65 words
The clock forwarding circuit as claimed in claim 1, wherein: the distributor outputs the delayed data transmitted via the data line to the data receiving latch when the semiconductor integrated circuit operates in a normal operational mode; and the distributor outputs the delayed send clock transmitted via the data line to the clock generator when the semiconductor integrated circuit operates in an abnormal operational mode.
Claim 10
Dependent Claim
18 words
The clock forwarding circuit as claimed in claim 8, wherein the abnormal operational mode is a power-up mode.
Claim 11
Dependent Claim
18 words
The clock forwarding circuit as claimed in claim 8, wherein the abnormal operational mode is an initialization mode.
Claim 12
Dependent Claim
90 words
The clock forwarding circuit as claimed in claim 1, wherein the clock generator comprises: a selector for selecting either the delayed send clock or the receive clock in response to the control signal; an AND gate for performing an AND operation on the output of the selector and the target clock; a NOR gate for performing a NOR operation on the output of the selector and the target clock; and a set-reset flip-flop for receiving the outputs of the AND gate and the NOR gate and generating the receive clock.
Claim 13
Independent Claim
100 words
A method of clock forwarding in a semiconductor integrated circuit, comprising the steps of: (a) latching data in response to a send clock; (b) outputting the send clock to a data line when the semiconductor integrated circuit operates in an abnormal operational mode; (c) receiving a target clock and a delayed send clock transmitted via the data line, and generating a receive clock therefrom; (d) outputting the latched data to the data line when the semiconductor integrated circuit operates in a normal operational mode; and (e) latching delayed data transmitted via the data line in response to the receive clock.
Claim 14
Independent Claim
100 words
A method of clock forwarding in a semiconductor integrated circuit, comprising the steps of: (a) latching data in response to a send clock; (b) outputting the send clock to a data line when the semiconductor integrated circuit operates in an abnormal operational mode; (c) receiving a target clock and a delayed send clock transmitted via the data line, and generating a receive clock therefrom; (d) outputting the latched data to the data line when the semiconductor integrated circuit operates in a normal operational mode; and (e) latching delayed data transmitted via the data line in response to the receive clock.
Claim 15
Dependent Claim
18 words
The clock forwarding method as claimed in claim 12, wherein the abnormal operational mode is a power-up mode.
Claim 16
Dependent Claim
18 words
The clock forwarding method as claimed in claim 12, wherein the abnormal operational mode is a initialization mode.
Claim 17
Dependent Claim
58 words
The clock forwarding method as claimed in claim 12, further comprising the steps of: between steps (b) and (c), applying the send clock output on the data line to a driver to drive the data line; and between steps (d) and (e), applying the data output on the data line to the driver to drive the data line.
Claim 18
Dependent Claim
31 words
The clock forwarding method as claimed in claim 12, further comprising, after step (e), in response to the target clock, again latching the data that was previously latched in step (e).
References Cited (Backward Citations)
US5452323A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-06 | 2003-06-07 | 2003-12-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-06 | 2007-06-07 | 2007-12-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-06 | 2011-06-07 | 2011-12-07 | $7700.00 | Window Closed / Lapsed |