US5452323A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Simple asynchronous data synchronizer to a faster clock
Assignee: Raytheon Co
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Filing: 1993-12-06
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Granted: 1995-09-19
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Expires: 2013-12-06
Abstract
Abstract A data synchronizer (10) for synchronizing data generated by a data source (16) at a first rate includes a first timer (22) for generating a first timing signal at the first rate. A first register (20) connected to the first timer (22) has an input connected to the data source (16). The first register (20) temporarily stores multi-bit data words from the date source (16). A second timer (26) generates a second timing signal at the second rate. A second register (24) connected to the second timer (26) has an input connected to an output of the first register (20). The second register (24) temporarily stores multi-bit data words from the first register (20). A synchronizer connected to the first and second timers (22, 26) generates a good data signal when the multi-bit data words from the first register (20) is available at an output of the second register (24).
Inventors
- 👤 Philip G. Rosen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:05
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
157 words
A data synchronizer for synchronizing data generated by a data source at a first rate to a second rate faster than said first rate, comprising: first timing means for generating a first timing signal at the first rate; first register means connected to the first timing means and having an input connected to said data source, said first register means for temporarily storing multi-bit data words from said data source; second timing means for generating a second timing signal at the second rate; second register means connected to the second timing means and having an input connected to an output of the first register means, said second register means for temporarily storing multi-bit data words from said first register means; and synchronizing means connected to said first and second timing means for generating a good data signal when said multi-bit data words from said first register means is available at an output of said second register means.
Claim 2
Dependent Claim
157 words
A data synchronizer for synchronizing data generated by a data source at a first rate to a second rate faster than said first rate, comprising: first timing means for generating a first timing signal at the first rate; first register means connected to the first timing means and having an input connected to said data source, said first register means for temporarily storing multi-bit data words from said data source; second timing means for generating a second timing signal at the second rate; second register means connected to the second timing means and having an input connected to an output of the first register means, said second register means for temporarily storing multi-bit data words from said first register means; and synchronizing means connected to said first and second timing means for generating a good data signal when said multi-bit data words from said first register means is available at an output of said second register means.
Claim 3
Dependent Claim
26 words
The data synchronizer of claim 1 wherein said synchronizing means further includes: third register means connected to said first timing means for generating a toggle signal.
Claim 4
Dependent Claim
26 words
The data synchronizer of claim 2 wherein the synchronizing means further includes: delay means connected to said third register means for generating a delayed toggle signal.
Claim 5
Dependent Claim
57 words
The data synchronizer of claim 3 wherein the delayed toggle signal provided by the delay means is related to the first rate minus the second rate, the time required to setup at least one of the first and second register means, and the time required to hold at least one of the first and second register means.
Claim 6
Dependent Claim
103 words
The data synchronizer of claim 4 wherein the synchronizing means further includes: a fourth register means connected to said second timing means and having an input connected to an output of said delay means; a fifth register means connected to said second timing means and having an input connected to an output of said fourth register means; and an exclusive OR gate having a first input connected to the output of said fourth register means and a second input connected to an output of said fifth register means, wherein said good data signal is generated at an output of said exclusive OR gate.
Claim 7
Dependent Claim
31 words
The data synchronizer of claim 5 wherein said synchronizing means further includes: control signal means for generating a control signal which enables said third register means to generate said toggle signal.
Claim 8
Dependent Claim
241 words
A data synchronizer for synchronizing data generated by a data source at a first rate to a second rate faster than said first rate, comprising: first timing means for generating a first timing signal at the first rate; first register means connected to the first timing means and having an input connected to said data source, said first register means for temporarily storing multi-bit data words from said data source; second timing means for generating a second timing signal at the second rate; second register means connected to the second timing means and having an input connected to an output of the first register means, said second register means for temporarily storing multi-bit data words from said first register means; and synchronizing means connected to said first and second timing means for generating a good data signal when said multi-bit data words from said first register means is available at an output of said second register means, said synchronizing means including: third register means connected to said first timing means for generating a toggle signal, and delay means connected to said third register means for generating a delayed toggle signal, wherein the delayed toggle signal provided by the delay means is related to the first rate minus the second rate, the time required to setup at least one of the first and second register means, and the time required to hold at least one of the first and second register means.
Claim 9
Dependent Claim
241 words
A data synchronizer for synchronizing data generated by a data source at a first rate to a second rate faster than said first rate, comprising: first timing means for generating a first timing signal at the first rate; first register means connected to the first timing means and having an input connected to said data source, said first register means for temporarily storing multi-bit data words from said data source; second timing means for generating a second timing signal at the second rate; second register means connected to the second timing means and having an input connected to an output of the first register means, said second register means for temporarily storing multi-bit data words from said first register means; and synchronizing means connected to said first and second timing means for generating a good data signal when said multi-bit data words from said first register means is available at an output of said second register means, said synchronizing means including: third register means connected to said first timing means for generating a toggle signal, and delay means connected to said third register means for generating a delayed toggle signal, wherein the delayed toggle signal provided by the delay means is related to the first rate minus the second rate, the time required to setup at least one of the first and second register means, and the time required to hold at least one of the first and second register means.
Claim 10
Dependent Claim
100 words
The data synchronizer of claim 7 wherein the synchronizing means further includes: a fourth register means connected to said second timing means and having an input connected to said delay means; a fifth register means connected to said second timing means and having an input connected to an output of said fourth register means; and an exclusive OR gate having a first input connected to the output of said fourth register means and a second input connected to an output of said fifth register means, wherein said good data signal is generated at an output of said exclusive OR gate.
Claim 11
Dependent Claim
327 words
A data synchronizer for synchronizing data generated by a data source at a first rate to a second rate faster than said first rate, comprising: first timing means for generating a first timing signal at the first rate; first register means connected to the first timing means and having an input connected to said data source, said first register means for temporarily storing multi-bit data words from said data source; second timing means for generating a second timing signal at the second rate; second register means connected to the second timing means and having an input connected to an output of the first register means, said second register means for temporarily storing multi-bit data words from said first register means; and synchronizing means connected to said first and second timing means for generating a good data signal when said multi-bit data words from said first register means is available at an output of said second register means, said synchronizing means including: third register means connected to said first timing means for generating a toggle signal, delay means connected to said third register means for generating a delayed toggle signal, wherein the delayed toggle signal provided by said delay means is related to the first rate minus the second rate, the time required to setup at least one of the first and second register means, and the time required to hold at least one of the first and second register means, a fourth register means connected to said second timing means and having an input connected to said delay means, a fifth register means connected to said second timing means and having an input connected to an output of said fourth register means, an exclusive OR gate having a first input connected to the output of said fourth register means and a second input connected to an output of said fifth register means, wherein said good data signal is generated at an output of said exclusive OR gate.
Claim 12
Dependent Claim
327 words
A data synchronizer for synchronizing data generated by a data source at a first rate to a second rate faster than said first rate, comprising: first timing means for generating a first timing signal at the first rate; first register means connected to the first timing means and having an input connected to said data source, said first register means for temporarily storing multi-bit data words from said data source; second timing means for generating a second timing signal at the second rate; second register means connected to the second timing means and having an input connected to an output of the first register means, said second register means for temporarily storing multi-bit data words from said first register means; and synchronizing means connected to said first and second timing means for generating a good data signal when said multi-bit data words from said first register means is available at an output of said second register means, said synchronizing means including: third register means connected to said first timing means for generating a toggle signal, delay means connected to said third register means for generating a delayed toggle signal, wherein the delayed toggle signal provided by said delay means is related to the first rate minus the second rate, the time required to setup at least one of the first and second register means, and the time required to hold at least one of the first and second register means, a fourth register means connected to said second timing means and having an input connected to said delay means, a fifth register means connected to said second timing means and having an input connected to an output of said fourth register means, an exclusive OR gate having a first input connected to the output of said fourth register means and a second input connected to an output of said fifth register means, wherein said good data signal is generated at an output of said exclusive OR gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-18 | 1999-03-20 | 1999-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-18 | 2003-03-20 | 2003-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-18 | 2007-03-20 | 2007-09-19 | $7700.00 | Window Closed / Lapsed |