Circuit for generating a signal with adjustable frequency

Claim 1

A circuit for generating a signal with adjustable frequency, comprising: a reference oscillator for generating a reference signal; a comparison signal device having an addition value input receiving an addition value signal and a clock input receiving a clock signal, said comparison signal device generating a digital comparison signal with a frequency dependent on the addition value signal present at said addition value input and on the clock signal present at said clock input; a phase comparator connected to receive the reference signal from said reference oscillator and the comparison signal from said comparison signal device, said phase comparator comparing a phase of the reference signal with a phase of the comparison signal and generating a tuning signal in dependence on a result of the comparison; an oscillator connected to said phase comparator and driven by the tuning signal, said oscillator generating an output signal of the circuit and an oscillator signal defining the clock signal present at said clock input of said comparison signal device; and said comparison signal device having an accumulator clocked by the clock signal and having a counter reading, said accumulator having a most significant bit and an overflow information item; wherein the comparison signal is derived from the counter reading of said accumulator, the comparison signal is derived from one of the most significant bit and the overflow information item of said accumulator, and instants of state changes in the digital comparison signal are subjected to jittering by comparison with clock instants of the clock signal.