US5351014A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Voltage control oscillator which suppresses phase noise caused by internal noise of the oscillator
Assignee: NEC Corp
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Filing: 1993-08-02
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Granted: 1994-09-27
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Expires: 2013-08-02
Abstract
Abstract A frequency synthesizer is composed of a reference oscillator, the first and the second integrators, a binary adder, a low pass filter and VCO forming a Phase Locked Loop (PLL). The first integrator, driven by the timing of a reference oscillator, integrates an externally supplied value K and generates the input signal. The second integrator, driven by the output signal of the VCO of the PLL, integrates an externally supplied value L. The binary adder detects the difference between the outputs of the first and the second integrators functioning as a phase comparator. The output of the phase comparator is converted into an analog voltage which is filtered to control the VCO to achieve frequency synthesis by the phase lock function of the loop.
Inventors
- 👤 Osamu Ichiyoshi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 07:20
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/1806; H03L7/08; H03L7/085
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
209 words
A frequency synthesizer in which a generated frequency signal is controlled by an externally provided numerical figure, comprising: a Q-bit binary numerical integration circuit that integrates a given numerical value K provided from the outside in the form of a Q-bit binary coded number by a Q-bit binary adder and a latch driven by the timing of a highly stable reference oscillator; a voltage-controlled oscillator (VCO) that generates an output signal with a frequency controlled by an applied control voltage as a reference frequency, a frequency divider that divides the frequency of the output of said VCO to generate a pulse signal output at a frequency proper for subsequent processings; a P-bit binary integration circuit that integrates a fixed numerical value L driven by the timing of the pulse signal output of said frequency divider; an R-bit binary adder that inputs the most significant R bits of said Q-bit binary integration circuit and of said P-bit binary integration circuit and outputs the difference therebetween; a D/A converter that converts a digital coded value of an output of said R-bit binary adder into an analog output voltage; and a low pass filter that smooths the analog output voltage of said D/A converter and provides the control voltage to the VCO.
Claim 2
Dependent Claim
209 words
A frequency synthesizer in which a generated frequency signal is controlled by an externally provided numerical figure, comprising: a Q-bit binary numerical integration circuit that integrates a given numerical value K provided from the outside in the form of a Q-bit binary coded number by a Q-bit binary adder and a latch driven by the timing of a highly stable reference oscillator; a voltage-controlled oscillator (VCO) that generates an output signal with a frequency controlled by an applied control voltage as a reference frequency, a frequency divider that divides the frequency of the output of said VCO to generate a pulse signal output at a frequency proper for subsequent processings; a P-bit binary integration circuit that integrates a fixed numerical value L driven by the timing of the pulse signal output of said frequency divider; an R-bit binary adder that inputs the most significant R bits of said Q-bit binary integration circuit and of said P-bit binary integration circuit and outputs the difference therebetween; a D/A converter that converts a digital coded value of an output of said R-bit binary adder into an analog output voltage; and a low pass filter that smooths the analog output voltage of said D/A converter and provides the control voltage to the VCO.
Claim 3
Dependent Claim
121 words
The frequency synthesizer of claim 1, further including a first monostable multivibrator that generates a binary logic output driven by the reference frequency, a second monostable multivibrator that generates a binary logic output driven by the pulse signal output of the frequency divider, an 0R logic device that generates a logical OR sum of output signals of said first and second monostable multivibrators, and a sample and hold circuit inserted between the D/A converter and the low pass filter that performs a track and hold function controlled by the output of the OR logic device, to inhibit noise that exists at the output of the D/A converter for a short period after each cycle of the VCO and the frequency divider.
Claim 4
Dependent Claim
51 words
The frequency synthesizer of claim 2, including means for connecting the D/A converter and the low pass filter while in a track state and for disconnecting the same while in a hold mode and for maintaining a previous voltage as an input to the low pass filter in the hold mode.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-26 | 1998-03-28 | 1998-09-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-26 | 2002-03-28 | 2002-09-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-26 | 2006-03-28 | 2006-09-27 | $7700.00 | Window Closed / Lapsed |