Technique for underfilling stacked chips on a cavity MLC module

Claim 1

An electronic device having enhanced mechanical, electrical and chemical reliability comprising an assembly of a plurality of stacked electrically connected integrated circuit chips having a top chip and a bottom chip, the top chip having a larger width and length and a larger surface area than other chips in a assembly and having peripheral non-bonded conductive pads thereon which peripheral pads are electrically connected to corresponding conductive pads on a surface of an interconnection substrate by solder connections between a corresponding set of pads, the interconnection substrate having a cavity having an open area smaller than the surface area of the top chip and an open area larger than the other chips which cavity accommodates and encloses the bottom chip and other chips of the assembly other than the top chip and wherein the cavity and solder connections between the chips and substrate are filled with an encapsulant by supplying an encapsulant material to the cavity through a through opening in the substrate which communicates with the cavity, the opening extending from a surface of the substrate to the cavity.