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US6226776B1
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System for converting hardware designs in high-level programming language to hardware implementations
Assignee: Synopsys Inc
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Filing: 1997-09-16
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Granted: 2001-05-01
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Expires: 2017-09-16
Abstract
Abstract A computer aided hardware design system for enabling design of an actual hardware implementation for a digital circuit using a high-level algorithmic programming language. The system converts an algorithmic representation for a hardware design initially created in the high-level programming language, such as ANSI C, to a hardware design implementation, such as an FPGA or other programmable logic or an ASIC. The C-type program representative of the hardware design is compiled into a register transfer level (RTL) hardware description language (HDL) that can be synthesized into a gate-level hardware representation. The system additionally enables simulation of the HDL design to verify design functionality. Finally, various physical design tools can be utilized to produce an actual hardware implementation. The system also permits the use of other non-C-type high-level programming languages by first translating to a C-type program. In contrast to previous hardware design tools, the system compiles all C-type programming language features, including pointers and structures, into synthesizable HDL.
Inventors
- 👤 Yuri V. Panchul
- 👤 Donald A. Soderman
- 👤 Denis R. Coleman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:47
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30
Claims Analysis
Total Claims: 64
Claim 1
Independent Claim
124 words
A method for converting a C-type language program to a hardware design, comprising the steps of: creating an algorithmic representation in a given C-type programming language corresponding to a preliminary hardware design; compiling the C-type programming language preliminary hardware design into a hardware description language (HDL) synthesizable design, wherein the step of compiling comprises the steps of: compiling a C-type program control flow into an HDL state machine; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; configuring in the HDL synthesizable design an interface for a gate-level hardware representation; determining the presence of any C-type pointers in the C-type program; and compiling any C-type pointers and pointer indirection into an HDL state-machine-based memory access protocol.
Claim 2
Independent Claim
124 words
A method for converting a C-type language program to a hardware design, comprising the steps of: creating an algorithmic representation in a given C-type programming language corresponding to a preliminary hardware design; compiling the C-type programming language preliminary hardware design into a hardware description language (HDL) synthesizable design, wherein the step of compiling comprises the steps of: compiling a C-type program control flow into an HDL state machine; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; configuring in the HDL synthesizable design an interface for a gate-level hardware representation; determining the presence of any C-type pointers in the C-type program; and compiling any C-type pointers and pointer indirection into an HDL state-machine-based memory access protocol.
Claim 3
Dependent Claim
29 words
The method of claim 1 , further comprising the step of synthesizing the HDL design into the gate-level hardware representation using a synthesis program to interpret the HDL design.
Claim 4
Dependent Claim
25 words
The method of claim 2 , further comprising the step of using physical design tools to implement the gate-level representation as an actual hardware implementation.
Claim 5
Dependent Claim
34 words
The method of claim 1 wherein the C-type programming language is selected from among the group of C-type programming languages consisting of ANSI C, B, C++, Java, Kernighan & Ritchie C, and Objective C.
Claim 6
Dependent Claim
30 words
The method of claim 1 wherein the hardware description language is selected from among the group of hardware description languages consisting of Verilog, VHDL, ABEL, CUPL, AHDL, MACHX, and PALASM.
Claim 7
Independent Claim
120 words
A method for converting a C-type language program to a hardware design, comprising the steps of: creating an algorithmic representation in a given C-type programming language corresponding to a preliminary hardware design; compiling the C-type programming lanauage preliminary hardware design into a hardware description language (HDL) synthesizable design, wherein the step of compiling comprises the steps of: compiling a C-type program control flow into an HDL state machine; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; configuring in the HDL synthesizable design an interface for a gate-level hardware representation; determining the presence of any non-addressable variables in the C-type program; and mapping any non-addressable variables onto hardware registers formed in HDL.
Claim 8
Independent Claim
120 words
A method for converting a C-type language program to a hardware design, comprising the steps of: creating an algorithmic representation in a given C-type programming language corresponding to a preliminary hardware design; compiling the C-type programming lanauage preliminary hardware design into a hardware description language (HDL) synthesizable design, wherein the step of compiling comprises the steps of: compiling a C-type program control flow into an HDL state machine; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; configuring in the HDL synthesizable design an interface for a gate-level hardware representation; determining the presence of any non-addressable variables in the C-type program; and mapping any non-addressable variables onto hardware registers formed in HDL.
Claim 9
Dependent Claim
25 words
The method of claim 6 wherein the C-type programming language variables include at least one of integer, floating point, pointer, enum, struct, and union variables.
Claim 10
Dependent Claim
29 words
The method of claim 6 , further comprising the step of synthesizing the HDL design into the gate-level hardware representation using a synthesis program to interpret the HDL design.
Claim 11
Dependent Claim
25 words
The method of claim 8 , further comprising the step of using physical design tools to implement the gate-level representation as an actual hardware implementation.
Claim 12
Dependent Claim
34 words
The method of claim 6 wherein the C-type programming language is selected from among the group of C-type programming languages consisting of ANSI C, B, C++, Java, Kernighan & Ritchie C, and Objective C.
Claim 13
Dependent Claim
30 words
The method of claim 6 wherein the hardware description language is selected from among the group of hardware description languages consisting of Verilog, VHDL, ABEL, CUPL, AHDL, MACHX, and PALASM.
Claim 14
Independent Claim
132 words
A method for converting a C-type language program to a hardware design, comprising the steps of: creating an algorithmic representation in a given C-type programming language corresponding to a preliminary hardware design; compiling the C-type programming language preliminary hardware design into a hardware description language (HDL) synthesizable design, wherein the step of compiling comprises the steps of: compiling a C-type program control flow into an HDL state machine; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; configuring in the HDL synthesizable design an interface for a gate-level hardware representation; determining the presence of any addressable variables in the C-type program; and mapping any addressable variables onto at least one of addressable hardware memory and an addressable array of hardware registers formed in HDL.
Claim 15
Independent Claim
132 words
A method for converting a C-type language program to a hardware design, comprising the steps of: creating an algorithmic representation in a given C-type programming language corresponding to a preliminary hardware design; compiling the C-type programming language preliminary hardware design into a hardware description language (HDL) synthesizable design, wherein the step of compiling comprises the steps of: compiling a C-type program control flow into an HDL state machine; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; configuring in the HDL synthesizable design an interface for a gate-level hardware representation; determining the presence of any addressable variables in the C-type program; and mapping any addressable variables onto at least one of addressable hardware memory and an addressable array of hardware registers formed in HDL.
Claim 16
Dependent Claim
25 words
The method of claim 12 wherein the C-type programming language variables include at least one of integer, floating point, pointer, enum, struct, and union variables.
Claim 17
Dependent Claim
29 words
The method of claim 12 , further comprising the step of synthesizing the HDL design into the gate-level hardware representation using a synthesis program to interpret the HDL design.
Claim 18
Dependent Claim
25 words
The method of claim 14 , further comprising the step of using physical design tools to implement the gate-level representation as an actual hardware implementation.
Claim 19
Dependent Claim
34 words
The method of claim 12 wherein the C-type programming language is selected from among the group of C-type programming languages consisting of ANSI C, B, C++, Java, Kernighan & Ritchie C, and Objective C.
Claim 20
Dependent Claim
30 words
The method of claim 12 wherein the hardware description language is selected from among the group of hardware description languages consisting of Verilog, VHDL, ABEL, CUPL, AHDL, MACHX, and PALASM.
Claim 21
Independent Claim
144 words
A method for converting a C-type language program to a hardware design, comprising the steps of: creating an algorithmic representation in a given C-type programming language corresponding to a preliminary hardware design; compiling the C-type programming language preliminary hardware design into a hardware description language (HDL) synthesizable design, wherein the step of compiling comprises the steps of: compiling a C-type program control flow into an HDL state machine; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; configuring in the HDL synthesizable design an interface for a gate-level hardware representation; determining the presence of any complicated C-type mathematical operations in the C-type program; and compiling multiple occurrences of any complicated C-type mathematical operation into a given HDL functional block that implements such an operation invoked on each occurrence by different states driven by the state machine.
Claim 22
Independent Claim
144 words
A method for converting a C-type language program to a hardware design, comprising the steps of: creating an algorithmic representation in a given C-type programming language corresponding to a preliminary hardware design; compiling the C-type programming language preliminary hardware design into a hardware description language (HDL) synthesizable design, wherein the step of compiling comprises the steps of: compiling a C-type program control flow into an HDL state machine; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; configuring in the HDL synthesizable design an interface for a gate-level hardware representation; determining the presence of any complicated C-type mathematical operations in the C-type program; and compiling multiple occurrences of any complicated C-type mathematical operation into a given HDL functional block that implements such an operation invoked on each occurrence by different states driven by the state machine.
Claim 23
Dependent Claim
29 words
The method of claim 18 , further comprising the step of synthesizing the HDL design into the gate-level hardware representation using a synthesis program to interpret the HDL design.
Claim 24
Dependent Claim
25 words
The method of claim 19 , further comprising the step of using physical design tools to implement the gate-level representation as an actual hardware implementation.
Claim 25
Dependent Claim
34 words
The method of claim 18 wherein the C-type programming language is selected from among the group of C-type programming languages consisting of ANSI C, B, C++, Java, Kernighan & Ritchie C, and Objective C.
Claim 26
Dependent Claim
30 words
The method of claim 18 wherein the hardware description language is selected from among the group of hardware description languages consisting of Verilog, VHDL, ABEL, CUPL, AHDL, MACHX, and PALASM.
Claim 27
Independent Claim
183 words
A method for converting a C-type language program to a hardware design, comprising the steps of: creating an algorithmic representation in a given C-type programming language corresponding to a preliminary hardware design; compiling the C-type programming language preliminary hardware design into a hardware description language (HDL) synthesizable design, wherein the step of compiling comprises the steps of: compiling a C-type program control flow into an HDL state machine; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; configuring in the HDL synthesizable design an interface for a gate-level hardware representation; and determining the presence of any recursion in the C-type program, and wherein at least one of an identifiable direct and indirect recursive function call is compiled into an HDL state machine which has an interface to a stack implemented utilizing one of external and internal memory and an array of hardware registers, wherein the state machine has a stack pointer implemented utilizing a hardware register employed to store and restore local variables of the recursive function and other recursive function information in the stack.
Claim 28
Independent Claim
183 words
A method for converting a C-type language program to a hardware design, comprising the steps of: creating an algorithmic representation in a given C-type programming language corresponding to a preliminary hardware design; compiling the C-type programming language preliminary hardware design into a hardware description language (HDL) synthesizable design, wherein the step of compiling comprises the steps of: compiling a C-type program control flow into an HDL state machine; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; configuring in the HDL synthesizable design an interface for a gate-level hardware representation; and determining the presence of any recursion in the C-type program, and wherein at least one of an identifiable direct and indirect recursive function call is compiled into an HDL state machine which has an interface to a stack implemented utilizing one of external and internal memory and an array of hardware registers, wherein the state machine has a stack pointer implemented utilizing a hardware register employed to store and restore local variables of the recursive function and other recursive function information in the stack.
Claim 29
Dependent Claim
29 words
The method of claim 23 , further comprising the step of synthesizing the HDL design into the gate-level hardware representation using a synthesis program to interpret the HDL design.
Claim 30
Dependent Claim
25 words
The method of claim 24 , further comprising the step of using physical design tools to implement the gate-level representation as an actual hardware implementation.
Claim 31
Dependent Claim
34 words
The method of claim 23 wherein the C-type programming language is selected from among the group of C-type programming languages consisting of ANSI C, B, C++, Java, Kernighan & Ritchie C, and Objective C.
Claim 32
Dependent Claim
30 words
The method of claim 23 wherein the hardware description language is selected from among the group of hardware description languages consisting of Verilog, VHDL, ABEL, CUPL, AHDL, MACHX, and PALASM.
Claim 33
Independent Claim
140 words
A method for converting a high-level language program to a hardware design, comprising the steps of: creating an algorithmic representation in a given high-level programming language corresponding to a preliminary hardware design; translating the high-level programming language preliminary hardware design into a C-type programming language preliminary hardware design; compiling the C-type programming language preliminary hardware design into a hardware description language (HDL) synthesizable design, wherein the step of compiling comprises the steps of: compiling a C-type program control flow into an HDL state machine; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; configuring in the HDL synthesizable design an interface for a gate-level hardware representation; determining the presence of any C-type pointers in the C-type program; and compiling any C-type pointers and pointer indirection into an HDL state-machine-based memory access protocol.
Claim 34
Independent Claim
140 words
A method for converting a high-level language program to a hardware design, comprising the steps of: creating an algorithmic representation in a given high-level programming language corresponding to a preliminary hardware design; translating the high-level programming language preliminary hardware design into a C-type programming language preliminary hardware design; compiling the C-type programming language preliminary hardware design into a hardware description language (HDL) synthesizable design, wherein the step of compiling comprises the steps of: compiling a C-type program control flow into an HDL state machine; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; configuring in the HDL synthesizable design an interface for a gate-level hardware representation; determining the presence of any C-type pointers in the C-type program; and compiling any C-type pointers and pointer indirection into an HDL state-machine-based memory access protocol.
Claim 35
Dependent Claim
29 words
The method of claim 28 , further comprising the step of synthesizing the HDL design into the gate-level hardware representation using a synthesis program to interpret the HDL design.
Claim 36
Dependent Claim
26 words
The method of claim 29 , further comprising the step of using physical design tools to implement the gate-level hardware representation as an actual hardware implementation.
Claim 37
Dependent Claim
73 words
The method of claim 28 wherein the high-level programming language is selected from among the group of C-type programming languages consisting of APL, Ada, Algol, B, Basic, Kernighan & Ritchie C, C++, CLOS, COBOL, Clu, Common Lisp, Coral, Dylan, Eiffel, Emacs Lisp, Forth, Fortran, IDL, Icon, Java, Jovial, Lisp, LOGO, ML, Modula, Oberon, Objective C, PL/I, PL/M, Pascal, Postscript, Prolog, Python, RTL, Rexx, SETL, Simula, Sather, Scheme, Smalltalk, Standard ML, TCL, and TRAC.
Claim 38
Dependent Claim
30 words
The method of claim 28 wherein the hardware description language is selected from among the group of hardware description languages consisting of Verilog, VHDL, ABEL, CUPL, AHDL, MACHX, and PALASM.
Claim 39
Independent Claim
136 words
A method for converting a high-level language program to a hardware design, comprising the steps of: creating an algorithmic representation in a given high-level programming language corresponding to a preliminary hardware design; translating the high-level programming language preliminary hardware design into a C-type programming language preliminary hardware design; compiling the C-type programming language preliminary hardware design into a hardware description language (HDL) synthesizable design, wherein the step of compiling comprises the steps of: compiling a C-type program control flow into an HDL state machine; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; configuring in the HDL synthesizable design an interface for a gate-level hardware representation; determining the presence of any non-addressable variables in the C-type program; and mapping any non-addressable variables onto hardware registers formed in HDL.
Claim 40
Independent Claim
136 words
A method for converting a high-level language program to a hardware design, comprising the steps of: creating an algorithmic representation in a given high-level programming language corresponding to a preliminary hardware design; translating the high-level programming language preliminary hardware design into a C-type programming language preliminary hardware design; compiling the C-type programming language preliminary hardware design into a hardware description language (HDL) synthesizable design, wherein the step of compiling comprises the steps of: compiling a C-type program control flow into an HDL state machine; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; configuring in the HDL synthesizable design an interface for a gate-level hardware representation; determining the presence of any non-addressable variables in the C-type program; and mapping any non-addressable variables onto hardware registers formed in HDL.
Claim 41
Dependent Claim
25 words
The method of claim 33 wherein the C-type programming language variables include at least one of integer, floating point, pointer, enum, struct, and union variables.
Claim 42
Dependent Claim
29 words
The method of claim 33 , further comprising the step of synthesizing the HDL design into the gate-level hardware representation using a synthesis program to interpret the HDL design.
Claim 43
Dependent Claim
26 words
The method of claim 35 , further comprising the step of using physical design tools to implement the gate-level hardware representation as an actual hardware implementation.
Claim 44
Dependent Claim
73 words
The method of claim 33 wherein the high-level programming language is selected from among the group of C-type programming languages consisting of APL, Ada, Algol, B, Basic, Kernighan & Ritchie C, C++, CLOS, COBOL, Clu, Common Lisp, Coral, Dylan, Eiffel, Emacs Lisp, Forth, Fortran, IDL, Icon, Java, Jovial, Lisp, LOGO, ML, Modula, Oberon, Objective C, PL/I, PL/M, Pascal, Postscript, Prolog, Python, RTL, Rexx, SETL, Simula, Sather, Scheme, Smalltalk, Standard ML, TCL, and TRAC.
Claim 45
Dependent Claim
30 words
The method of claim 33 wherein the hardware description language is selected from among the group of hardware description languages consisting of Verilog, VHDL, ABEL, CUPL, AHDL, MACHX, and PALASM.
Claim 46
Independent Claim
148 words
A method for converting a high-level language program to a hardware design, comprising the steps of: creating an algorithmic representation in a given high-level programming language corresponding to a preliminary hardware design; translating the high-level programming language preliminary hardware design into a C-type programming language preliminary hardware design; compiling the C-type programming language preliminary hardware design into a hardware description language (HDL) synthesizable design, wherein the step of compiling comprises the steps of: compiling a C-type program control flow into an HDL state machine; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; configuring in the HDL synthesizable design an interface for a gate-level hardware representation; determining the presence of any addressable variables in the C-type program; and mapping any addressable variables onto at least one of addressable hardware memory and an addressable array of hardware registers formed in HDL.
Claim 47
Independent Claim
148 words
A method for converting a high-level language program to a hardware design, comprising the steps of: creating an algorithmic representation in a given high-level programming language corresponding to a preliminary hardware design; translating the high-level programming language preliminary hardware design into a C-type programming language preliminary hardware design; compiling the C-type programming language preliminary hardware design into a hardware description language (HDL) synthesizable design, wherein the step of compiling comprises the steps of: compiling a C-type program control flow into an HDL state machine; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; configuring in the HDL synthesizable design an interface for a gate-level hardware representation; determining the presence of any addressable variables in the C-type program; and mapping any addressable variables onto at least one of addressable hardware memory and an addressable array of hardware registers formed in HDL.
Claim 48
Dependent Claim
25 words
The method of claim 39 wherein the C-type programming language variables include at least one of integer, floating point, pointer, enum, struct, and union variables.
Claim 49
Dependent Claim
29 words
The method of claim 39 , further comprising the step of synthesizing the HDL design into the gate-level hardware representation using a synthesis program to interpret the HDL design.
Claim 50
Dependent Claim
26 words
The method of claim 41 , further comprising the step of using physical design tools to implement the gate-level hardware representation as an actual hardware implementation.
Claim 51
Dependent Claim
74 words
The method of claim 39 , wherein the high-level programming language is selected from among the group of C-type programming languages consisting of APL, Ada, Algol, B, Basic, Kernighan & Ritchie C, C++, CLOS, COBOL, Clu, Common Lisp, Coral, Dylan, Eiffel, Emacs Lisp, Forth, Fortran, IDL, Icon, Java, Jovial, Lisp, LOGO, ML, Modula, Oberon, Objective C, PL/I, PL/M, Pascal, Postscript, Prolog, Python, RTL, Rexx, SETL, Simula, Sather, Scheme, Smalltalk, Standard ML, TCL, and TRAC.
Claim 52
Dependent Claim
30 words
The method of claim 39 wherein the hardware description language is selected from among the group of hardware description languages consisting of Verilog, VHDL, ABEL, CUPL, AHDL, MACHX, and PALASM.
Claim 53
Independent Claim
160 words
A method for converting a high-level language program to a hardware design, comprising the steps of: creating an algorithmic representation in a given high-level programming language corresponding to a preliminary hardware design; translating the high-level programming language preliminary hardware design into a C-type programming language preliminary hardware design; compiling the C-type programming language preliminary hardware design into a hardware description language (HDL) synthesizable design, wherein the step of compiling comprises the steps of: compiling a C-type program control flow into an HDL state machine; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; configuring in the HDL synthesizable design an interface for a gate-level hardware representation; determining the presence of any complicated C-type mathematical operations in the C-type program; and compiling multiple occurrences of any complicated C-type mathematical operation into a given HDL functional block that implements such an operation invoked on each occurrence by different states driven by the state machine.
Claim 54
Independent Claim
160 words
A method for converting a high-level language program to a hardware design, comprising the steps of: creating an algorithmic representation in a given high-level programming language corresponding to a preliminary hardware design; translating the high-level programming language preliminary hardware design into a C-type programming language preliminary hardware design; compiling the C-type programming language preliminary hardware design into a hardware description language (HDL) synthesizable design, wherein the step of compiling comprises the steps of: compiling a C-type program control flow into an HDL state machine; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; configuring in the HDL synthesizable design an interface for a gate-level hardware representation; determining the presence of any complicated C-type mathematical operations in the C-type program; and compiling multiple occurrences of any complicated C-type mathematical operation into a given HDL functional block that implements such an operation invoked on each occurrence by different states driven by the state machine.
Claim 55
Dependent Claim
29 words
The method of claim 45 , further comprising the step of synthesizing the HDL design into the gate-level hardware representation using a synthesis program to interpret the HDL design.
Claim 56
Dependent Claim
26 words
The method of claim 46 , further comprising the step of using physical design tools to implement the gate-level hardware representation as an actual hardware implementation.
Claim 57
Dependent Claim
73 words
The method of claim 45 wherein the high-level programming language is selected from among the group of C-type programming languages consisting of APL, Ada, Algol, B, Basic, Kernighan & Ritchie C, C++, CLOS, COBOL, Clu, Common Lisp, Coral, Dylan, Eiffel, Emacs Lisp, Forth, Fortran, IDL, Icon, Java, Jovial, Lisp, LOGO, ML, Modula, Oberon, Objective C, PL/I, PL/M, Pascal, Postscript, Prolog, Python, RTL, Rexx, SETL, Simula, Sather, Scheme, Smalltalk, Standard ML, TCL, and TRAC.
Claim 58
Dependent Claim
30 words
The method of claim 45 wherein the hardware description language is selected from among the group of hardware description languages consisting of Verilog, VHDL, ABEL, CUPL, AHDL, MACHX, and PALASM.
Claim 59
Independent Claim
199 words
A method for converting a high-level language program to a hardware design, comprising the steps of: creating an algorithmic representation in a given high-level programming language corresponding to a preliminary hardware design; translating the high-level programming language preliminary hardware design into a C-type programming language preliminary hardware design; compiling the C-type programming language preliminary hardware design into a hardware description language (HDL) synthesizable design, wherein the step of compiling comprises the steps of: compiling a C-type program control flow into an HDL state machine; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; configuring in the HDL synthesizable design an interface for a gate-level hardware representation; and determining the presence of any recursion in the C-type program, and wherein at least one of an identifiable direct and indirect recursive function call is compiled into an HDL state machine which has an interface to a stack implemented utilizing one of external and internal memory and an array of hardware registers, wherein the state machine has a stack pointer implemented utilizing a hardware register employed to store and restore local variables of the recursive function and other recursive function information in the stack.
Claim 60
Independent Claim
199 words
A method for converting a high-level language program to a hardware design, comprising the steps of: creating an algorithmic representation in a given high-level programming language corresponding to a preliminary hardware design; translating the high-level programming language preliminary hardware design into a C-type programming language preliminary hardware design; compiling the C-type programming language preliminary hardware design into a hardware description language (HDL) synthesizable design, wherein the step of compiling comprises the steps of: compiling a C-type program control flow into an HDL state machine; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; configuring in the HDL synthesizable design an interface for a gate-level hardware representation; and determining the presence of any recursion in the C-type program, and wherein at least one of an identifiable direct and indirect recursive function call is compiled into an HDL state machine which has an interface to a stack implemented utilizing one of external and internal memory and an array of hardware registers, wherein the state machine has a stack pointer implemented utilizing a hardware register employed to store and restore local variables of the recursive function and other recursive function information in the stack.
Claim 61
Dependent Claim
29 words
The method of claim 50 , further comprising the step of synthesizing the HDL design into the gate-level hardware representation using a synthesis program to interpret the HDL design.
Claim 62
Dependent Claim
26 words
The method of claim 51 , further comprising the step of using physical design tools to implement the gate-level hardware representation as an actual hardware implementation.
Claim 63
Dependent Claim
73 words
The method of claim 50 wherein the high-level programming language is selected from among the group of C-type programming languages consisting of APL, Ada, Algol, B, Basic, Kernighan & Ritchie C, C++, CLOS, COBOL, Clu, Common Lisp, Coral, Dylan, Eiffel, Emacs Lisp, Forth, Fortran, IDL, Icon, Java, Jovial, Lisp, LOGO, ML, Modula, Oberon, Objective C, PL/I, PL/M, Pascal, Postscript, Prolog, Python, RTL, Rexx, SETL, Simula, Sather, Scheme, Smalltalk, Standard ML, TCL, and TRAC.
Claim 64
Dependent Claim
30 words
The method of claim 50 wherein the hardware description language is selected from among the group of hardware description languages consisting of Verilog, VHDL, ABEL, CUPL, AHDL, MACHX, and PALASM.
References Cited (Backward Citations)
US5197016A
Cited
US5748488A
Cited
US5437037A
Cited
US5603043A
Cited
US5530843A
Cited
US5493507A
Cited
US5953519A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2004-04-30 | 2004-10-30 | 2005-05-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-04-30 | 2008-10-30 | 2009-05-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-04-30 | 2012-10-30 | 2013-05-01 | $7700.00 | Window Closed / Lapsed |