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US6225834B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Bit line sense amplifier

Assignee: SK Hynix Inc
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Filing: 1999-12-21
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Granted: 2001-05-01
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Expires: 2019-12-21
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Abstract

Abstract The present invention relates to a bit line sense amplifier for a semiconductor memory device, and in particular to a data sense amplifier which can increase a data sensing speed and improve an operational speed of a chip by using a current sensing method in data-sensing a bit line having a large capacitive load. The bit line sense amplifier according to the present invention includes: a switch unit interrupting a capacitive load of the bit line; a charging current generating unit rapidly generating a charging current to a sense amp output terminal; and an output potential control unit rapidly converting a potential of the sense amp output terminal to a ground voltage level or a power voltage level. As a result, even if a large capacitive load is applied to the bit line, a high-speed charging operation can be carried out, thereby improving the operational speed of the chip.

Inventors

  • 👤 Yung Jin Gang

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 23:02
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/065; H; H10; H10D; H10D84/00

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 269 words
In a cross-coupled latch type bit line sense amplifier, a bit line sense amplifier comprises: a first switch unit operated according to a sense amp enable signal, and interrupting a capacitive load of one-side bit line from a sense amp one-side output terminal in a sensing operation; a first charging current generating unit turned on by a precharge voltage of the one-side bit line, and rapidly outputting a charging current generated from the sense amp enable signal to the sense amp one-side output terminal; a second switch unit operated according to the sense amp enable signal, and interrupting a capacitive load of the other-side bit line from a sense amp other-side output terminal in the sensing operation; a second charging current generating unit turned on by a precharge voltage of the other-side bit line, and rapidly outputting the charging current generated from the sense amp enable signal to the sense amp other-side output terminal; a first output potential control unit and a second output potential control unit connected between an output terminal of the charging current generating unit and an input terminal of a sense amp control signal, and rapidly converting potentials of each sense amp output terminal to a ground voltage level in the sensing operation; a capacitor connected between the one-side output terminal of the sense amplifier and the ground, and charging the charging current; and a cross-coupled latch unit, connected between the output terminal of the charging current generating unit and the input terminal of the sense amp control signal, and rapidly converting the potential of the sense amp output terminal to a power voltage level.
Claim 2
Dependent Claim 269 words
In a cross-coupled latch type bit line sense amplifier, a bit line sense amplifier comprises: a first switch unit operated according to a sense amp enable signal, and interrupting a capacitive load of one-side bit line from a sense amp one-side output terminal in a sensing operation; a first charging current generating unit turned on by a precharge voltage of the one-side bit line, and rapidly outputting a charging current generated from the sense amp enable signal to the sense amp one-side output terminal; a second switch unit operated according to the sense amp enable signal, and interrupting a capacitive load of the other-side bit line from a sense amp other-side output terminal in the sensing operation; a second charging current generating unit turned on by a precharge voltage of the other-side bit line, and rapidly outputting the charging current generated from the sense amp enable signal to the sense amp other-side output terminal; a first output potential control unit and a second output potential control unit connected between an output terminal of the charging current generating unit and an input terminal of a sense amp control signal, and rapidly converting potentials of each sense amp output terminal to a ground voltage level in the sensing operation; a capacitor connected between the one-side output terminal of the sense amplifier and the ground, and charging the charging current; and a cross-coupled latch unit, connected between the output terminal of the charging current generating unit and the input terminal of the sense amp control signal, and rapidly converting the potential of the sense amp output terminal to a power voltage level.
Claim 3
Dependent Claim 36 words
The bit line sense amplifier according to claim 1 , wherein the first switch unit and the second switch unit respectively comprise a MOS transistor having its gate connected to receive the sense amp enable signal.
Claim 4
Dependent Claim 49 words
The bit line sense amplifier according to claim 1 , wherein the first charging current generating unit and the second charging current generating unit comprise lateral bipolar junction transistors having their bases connected to one-side bit line and the other-side bit line, respectively, and existing below the MOS transistor.
Claim 5
Dependent Claim 71 words
The bit line sense amplifier according to claim 1 , wherein the first output potential control unit and the second output potential control unit respectively comprise a gate-base-body connected hybrid transistor consisting of a MOS transistor having its gate connected to receive the power voltage, and a bipolar junction transistor having its base connected to receive the ground voltage, the MOS transistor and the bipolar junction transistor being connected in parallel.
Claim 6
Dependent Claim 29 words
The bit line sense amplifier according to claim 4 , wherein the MOS transistor comprises an NMOS transistor, and the bipolar junction transistor comprises an NPN bipolar junction transistor.
Claim 7
Dependent Claim 29 words
The bit line sense amplifier according to claim 4 , wherein the MOS transistor comprises a PMOS transistor, and the bipolar junction transistor comprises a PNP bipolar junction transistor.

References Cited (Backward Citations)

US4896196A Cited
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US5670388A Cited
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US5804992A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-04-30 2004-10-30 2005-05-01 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2008-04-30 2008-10-30 2009-05-01 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2012-04-30 2012-10-30 2013-05-01 $7700.00 Window Closed / Lapsed

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