US5670388A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making contacted body silicon-on-insulator field effect transistor
Assignee: GlobalFoundries Inc
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Filing: 1995-10-13
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Granted: 1997-09-23
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Expires: 2015-10-13
Abstract
Abstract Structures and methods are presented for forming a body-substrate connector for an SOI FET. The connector is formed substantially co-aligned with the gate conductor on a side of the device that does not interfere with source and drain. The body is thus held close to the substrate potential and the connector provides a path for majority carriers to quickly leave the body. By contacting the body of the SOI MOSFET device in a manner that does not perturb the charge imaged by the gate, parasitic bipolar effects are eliminated while maintaining the desirable attributes of SOI MOSFET devices, such as low substrate bias sensitivity and steep sub-threshold slope. By forming the connector substantially co-aligned with the gate conductor the connection uses little or no surface area.
Inventors
- 👤 Brian John Machesney
- 👤 Jack Allan Mandelman
- 👤 Edward Joseph Nowak
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:24
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/201; Y; Y10; Y10S; Y10S148/00; Y10S148/15; Y10S438/00; Y10S438/98
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
126 words
A method of forming a silicon-on-insulator FET comprising the steps of: a) providing a semiconductor substrate having a buried dielectric, said buried dielectric defining lower and upper regions of said substrate; b) forming a connection between said lower and upper regions of said substrate; c) forming a gate dielectric on said upper region; d) forming a gate on said gate dielectric, said gate having a first side, a second side, and a third side; and e) forming a source and a drain in said upper region and leaving a body therebetween, wherein said source is aligned to said first side and said drain is aligned to said second side; wherein said step (b) involves forming said connection substantially co-aligned with said third side of said gate.
Claim 2
Independent Claim
126 words
A method of forming a silicon-on-insulator FET comprising the steps of: a) providing a semiconductor substrate having a buried dielectric, said buried dielectric defining lower and upper regions of said substrate; b) forming a connection between said lower and upper regions of said substrate; c) forming a gate dielectric on said upper region; d) forming a gate on said gate dielectric, said gate having a first side, a second side, and a third side; and e) forming a source and a drain in said upper region and leaving a body therebetween, wherein said source is aligned to said first side and said drain is aligned to said second side; wherein said step (b) involves forming said connection substantially co-aligned with said third side of said gate.
Claim 3
Dependent Claim
33 words
A method as recited in claim 1, wherein said step (b) involves forming said connection so that its position with respect to the gate does not prevent said body from reaching full depletion.
Claim 4
Dependent Claim
36 words
A method as recited in claim 1, wherein said step (b) involves forming said connection so that said connection is spaced from said third side of said gate by a distance of less than 200 nm.
Claim 5
Dependent Claim
35 words
A method as recited in claim 1, wherein said step (a) involves forming two adjacent buried dielectrics and said step (b) involves forming said connection by leaving a gap between said two adjacent buried dielectrics.
Claim 6
Dependent Claim
32 words
A method as recited in claim 1, wherein said step (b) involves forming said connection so that said connection is formed directly below insulation that is substantially thicker than said gate insulator.
Claim 7
Dependent Claim
54 words
A method as recited in claim 1, wherein said gate electrode has an electric field when said FET is in normal operation and wherein said step (b) involves forming said connection to a portion of said upper region in which the electric field is substantially smaller than the electric field under said gate electrode.
Claim 8
Dependent Claim
45 words
A method as recited in claim 1, comprising the steps of forming said upper region with a thickness, said body with a doping, and said gate conductor with a work function so that said body is fully depleted when said FET is in normal operation.
Claim 9
Dependent Claim
27 words
A method as recited in claim 1, wherein said step (a) involves providing an upper region with a thickness in the range 5 nm to 500 nm.
Claim 10
Dependent Claim
61 words
A method as recited in claim 1, wherein said step (a) involves forming said upper region by providing a silicon wafer having a first and a second major surface and having a blanket oxide over said first major surface, mounting said first major surface on a support substrate, and etching said second major surface until the silicon is a specified thickness.
Claim 11
Dependent Claim
36 words
A method as recited in claim 1, wherein said step (a) involves forming said buried dielectric by one of depositing an insulator in a horizontal trench, thermally oxidizing silicon in a horizontal trench, and forming SIMOX.
Claim 12
Dependent Claim
30 words
A method as recited in claim 10, wherein said horizontal trench is formed by implanting a dopant, forming a vertical trench intersecting said dopant, and providing a dopant preferential etch.
Claim 13
Dependent Claim
16 words
A method as recited in claim 11, further comprising lining said vertical trench with said insulator.
Claim 14
Dependent Claim
21 words
A method as recited in claim 1, wherein said step (a) involves initially forming said buried dielectric as a blanket layer.
Claim 15
Dependent Claim
28 words
A method as recited in claim 1, wherein said step (a) and said step (d) involve forming said buried dielectric and said gate of said FET substantially co-aligned.
Claim 16
Dependent Claim
67 words
A method as recited in claim 1, wherein said step (a) involves forming said buried dielectric so that said buried dielectric is self-aligned to a first edge, and wherein said step (b) involves forming said connection so that said connection is self-aligned to said first edge, and wherein said step (c) involves forming said gate dielectric so that said gate dielectric is self-aligned to said first edge.
Claim 17
Dependent Claim
24 words
A method as recited in claim 15, wherein said edge is defined by a spacer located adjacent to a photolithographically formed thick oxide layer.
Claim 18
Dependent Claim
77 words
A method as recited in claim 1, further comprising between steps (a) and (b), a1) forming on said substrate an insulating layer formed from a first material with first etch properties; a2) forming a pattern in said insulating layer having substantially vertical sidewalls; a3) providing spacers adjacent said sidewalls, said spacers formed from a second material with second etch properties; and wherein said step (c) involves forming said gate dielectric on said upper region between said spacers.
Claim 19
Dependent Claim
37 words
A method as recited in claim 17, wherein said step (a) involves forming said buried dielectric so that said buried dielectric is formed self-aligned to said spacers by ion implantation of one of oxygen and a dopant.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-22 | 2001-03-24 | 2001-09-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-22 | 2005-03-24 | 2005-09-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-22 | 2009-03-24 | 2009-09-23 | $7700.00 | Window Closed / Lapsed |