Silicon-on-insulator H-transistor layout for gate arrays

Claim 2

An integrated circuit gate array device formed within a layer of silicon disposed over an insulator film located on top of a silicon substrate comprising: a. at least two H-transistors arranged in a column-like design, wherein the column-like design has a top portion, a mid portion, and a bottom portion, wherein each H-transistor comprises: i. a gate comprised of two substantially parallel, elongated members and an integrally attached cross member; ii. a channel region, the cross member disposed over the channel region; iii. a gate insulator region disposed between the cross member and the channel region; iv. a source region located to one side of the cross member and between the parallel members; v. a drain region located to the other side of the cross member and between the parallel members; and vi. two well regions having a predetermined doping concentration, each well region abutting a parallel, elongated member of the gate; b. a first region of insulator at substantially the top of the column-like design; c. a second region of insulator located between adjacent transistors in a column at substantially the midpoint of the column-like design; and d. a third region of insulator which terminates at substantially the bottom portion of the column-like design.

Claim 3

The gate array of claim 1, wherein at least one transistor is sufficiently doped to create an N channel device.

Claim 4

The gate array of claim 1, wherein at least one transistor is sufficiently doped to create a P channel device.

Claim 5

The gate array of claim 1, wherein each transistor is flanked on both sides by a corresponding elongated region of insulator.

Claim 6

The insulator of claim 4, wherein each elongated insulator region overlies an elongated trench.

Claim 7

The gate array of claim 1, wherein a plurality of transistors are arranged in a column.

Claim 8

The gate array of claim 5, wherein a plurality of transistors are arranged in at least two rows.

Claim 9

The gate array of claim 1, wherein the transistors within a column are all of the same type.

Claim 10

The gate array of claim 7, wherein the transistors within a row are of alternating types.

Claim 11

The gate array of claim 6, wherein all the transistors within a column are N type.

Claim 12

The gate array of claim 6, wherein all the transistors within a column are P type.

Claim 13

The gate array of claim 1, wherein the insulator regions located at substantially the column's top, mid, and bottom portions are comprised of field oxide.

Claim 14

The gate array of claim 1, wherein the insulator film is comprised of silicon dioxide.

Claim 15

The gate array of claim 1, wherein the insulator film is comprised of sapphire.

Claim 16

The gate array of claim 1, wherein the insulator film is comprised of spinel.

Claim 17

An integrated circuit gate array device formed within a layer of silicon disposed over an insulator film located on top of a silicon substrate comprising: a. a plurality of H-transistors arranged in a matrix-like design, wherein each matrix has at least two columns and at least two rows, wherein each column has a top portion, a mid portion, and a bottom portion, wherein each transistor comprises: i. a gate comprised of two substantially parallel, elongated members and an integrally attached cross member; ii. a channel region, the cross member disposed over the channel region; iii. a gate insulator region disposed between the cross member and the channel region; iv. a source region located to one side of the cross member and between the parallel members; v. a drain region located to the other side of the cross member and between the parallel members; and vi. two well regions having a predetermined doping concentration, each well region abutting a portion of a corresponding parallel, elongated member of the gate; b. a first region of insulator located at substantially the top of each column; c. a second region of insulator located between the adjacent transistors in a column at substantially the midpoint of each column; d. a third region of insulator located at substantially the bottom of each column; and e. wherein each transistor is flanked on both sides by a corresponding elongated insulator region oriented parallel to the associated well region.

Claim 18

An integrated circuit gate array device formed within a layer of silicon disposed over an insulator film located on top of a silicon substrate comprising: a. a plurality of H-transistors arranged in a matrix-like design, wherein each matrix has at least two columns and at least two rows, wherein each column has a top portion, a mid portion, and a bottom portion, wherein each transistor comprises: i. a gate comprised of two substantially parallel, elongated members and an integrally attached cross member; ii. a channel region, the cross member disposed over the channel region; iii. a gate insulator region disposed between the cross member and the channel region; iv. a source region located to one side of the cross member and between the parallel members; v. a drain region located to the other side of the cross member and between the parallel members; and vi. two well regions having a predetermined doping concentration, each well region abutting a portion of a corresponding parallel, elongated member of the gate; b. a first region of insulator located at substantially the top of each column; c. a second region of insulator located between the adjacent transistors in a column at substantially the midpoint of each column; d. a third region of insulator located at substantially the bottom of each column; and e. wherein each transistor is flanked on both sides by a corresponding elongated insulator region oriented parallel to the associated well region.

Claim 19

The gate array of claim 16, wherein at least one transistor is sufficiently doped to create an N channel device.

Claim 20

The gate array of claim 16, wherein at least one transistor is sufficiently doped to create a P channel device.

Claim 21

The gate array of claim 16, wherein each of the elongated regions of insulator overlies a corresponding elongated trench.

Claim 22

The gate array of claim 16, wherein the transistors within a column are all of the same type.

Claim 23

The gate array of claim 16, wherein the transistors within a row of alternating types.

Claim 24

The gate array of claim 16, wherein all the transistors within a column are N type.

Claim 25

The gate array of claim 16, wherein all the transistors within a column are P type.

Claim 26

The gate array of claim 16, wherein the insulator regions located at the column's top, mid, and bottom portions are comprised of field oxide.

Claim 27

The gate array of claim 16, wherein the insulator film is comprised of silicon dioxide.

Claim 28

The gate array of claim 16, wherein the insulator film is comprised of sapphire.

Claim 29

The gate array of claim 15, wherein the insulator film is comprised of spinel.

Claim 30

An integrated circuit gate array device formed within a layer of silicon disposed over an insulator film located on top of a silicon substrate comprising: a. at least two H-transistors arranged in a column-like design, wherein the column has a top portion, a mid portion, and a bottom portion, wherein each transistor comprises: i. a gate comprised of two substantially parallel, elongated members and an integrally attached cross member; ii. a channel region, the cross member disposed over the channel region; iii. a gate insulator region disposed between the cross member and the channel region; iv. a source region located to one side of the intersection of the cross member and between the parallel members; v. a drain region located to the other side of the cross member and between the parallel members; and vi. two well regions having a predetermined doping concentration, each well region abutting a portion of a corresponding, parallel, elongated member of the gate; b. a first region of insulator located at substantially the top of the column-like design; c. a second region of insulator located between adjacent transistors in the column at substantially the midpoint of each column; d. a third region of insulator located at substantially the bottom of each column; and e. wherein each transistor is flanked on both sides by a corresponding elongated insulator region oriented parallel to the associated well region.

Claim 31

An integrated circuit gate array device formed within a layer of silicon disposed over an insulator film located on top of a silicon substrate comprising: a. at least two H-transistors arranged in a column-like design, wherein the column has a top portion, a mid portion, and a bottom portion, wherein each transistor comprises: i. a gate comprised of two substantially parallel, elongated members and an integrally attached cross member; ii. a channel region, the cross member disposed over the channel region; iii. a gate insulator region disposed between the cross member and the channel region; iv. a source region located to one side of the intersection of the cross member and between the parallel members; v. a drain region located to the other side of the cross member and between the parallel members; and vi. two well regions having a predetermined doping concentration, each well region abutting a portion of a corresponding, parallel, elongated member of the gate; b. a first region of insulator located at substantially the top of the column-like design; c. a second region of insulator located between adjacent transistors in the column at substantially the midpoint of each column; d. a third region of insulator located at substantially the bottom of each column; and e. wherein each transistor is flanked on both sides by a corresponding elongated insulator region oriented parallel to the associated well region.

Claim 32

The gate array architecture of claim 28, wherein at least one transistor is sufficiently doped to create an N channel device.

Claim 33

The gate array architecture of claim 28, wherein at least one transistor is sufficiently doped to create an P channel device.

Claim 34

The gate array of claim 28, wherein each of the elongated regions of insulator overlies a corresponding elongated trench.

Claim 35

The gate array of claim 31, wherein a plurality of transistors are arranged in a column.

Claim 36

The gate array of claim 31, wherein a plurality of transistors are arranged in at least two rows.

Claim 37

The gate array of claim 32, wherein the transistors within a column are all of the same type.

Claim 38

The gate array of claim 31, wherein the transistors within a row are of alternating types.

Claim 39

The gate array of claim 32, wherein all the transistors within a column are N type.

Claim 40

The gate array of claim 32, wherein all the transistors within a column are P type.

Claim 41

The gate array of claim 28, wherein the insulator regions located at the column's top, mid, and bottom portions are comprised of field oxide.

Claim 42

The gate array of claim 28, wherein the insulator film is comprised of silicon dioxide.

Claim 43

The gate array of claim 28, wherein the insulator film is comprised of sapphire.

Claim 44

The gate array of claim 28, wherein the insulator film is comprised of spinel.