Patent US6208542B1 successfully refreshed from Google Patents.
US6208542B1
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Techniques for storing digital data in an analog or multilevel memory
Assignee: SanDisk Corp
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Filing: 1999-06-02
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Granted: 2001-03-27
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Expires: 2019-06-02
Abstract
Abstract An integrated circuit stores analog or digital information, or both, in memory cells (416). The memory cells provide analog or multilevel storage. Analog information is provided through an analog signal input (405), and digital information is provided through a digital signal input (407). A scheme for storing digital information is consistent with the scheme used to store analog information. Data is retrieved from the memory cells, and output to the analog or digital signal output (454, 463) depending on the type of data. A digital reference generator reference generator (425) generates various analog equivalent voltages for the digital signal input.
Inventors
- 👤 Cheng-Yuan Michael Wang
- 👤 Andreas M. Haeberli
- 👤 Carl W. Werner
- 👤 Sau C. Wong
- 👤 Hock C. So
- 👤 Leon Sea Jiunn Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:29
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5621; G11C11/5642; G11C11/5628; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12; G11C16/30; G11C16/32; G11C27/00; G11C27/005; G11C27/02; G11C27/024; G11C27/026; G11C5/00; G11C5/14; G11C5/145; G11C7/00; G11C7/16
Claims Analysis
Total Claims: 41
Claim 1
Independent Claim
94 words
A method of storing information in a memory comprising the steps of: providing an analog signal at an analog signal input; providing digital data at a digital signal input; providing an array of memory cells; sampling the analog signal input at a user-selected sampling frequency; storing samples of the analog signal in the array of memory cells, wherein a memory cell holds at least one sample of the analog signal; and storing the digital data in the array of memory cells, wherein a memory cell holds at least a bit of the digital data.
Claim 2
Independent Claim
94 words
A method of storing information in a memory comprising the steps of: providing an analog signal at an analog signal input; providing digital data at a digital signal input; providing an array of memory cells; sampling the analog signal input at a user-selected sampling frequency; storing samples of the analog signal in the array of memory cells, wherein a memory cell holds at least one sample of the analog signal; and storing the digital data in the array of memory cells, wherein a memory cell holds at least a bit of the digital data.
Claim 3
Dependent Claim
18 words
The method of claim 1 wherein a memory cell holds at least two bits of the digital data.
Claim 4
Dependent Claim
18 words
The method of claim 1 wherein a memory cell holds at least six bits of the digital data.
Claim 5
Dependent Claim
23 words
The method of claim 1 further comprising the step of: serially clocking and storing the digital data into the array of memory cells.
Claim 6
Dependent Claim
24 words
The method of claim 1 further comprising the step of: providing a command at the digital signal input to select the user-selected sampling frequency.
Claim 7
Dependent Claim
33 words
The method of claim 1 wherein each memory cell in the array capable of storing analog data from the analog signal input is capable of storing digital data from the digital signal input.
Claim 8
Dependent Claim
34 words
The method of claim 1 further comprising the step of: converting the digital data into an analog equivalent representation, wherein storing the digital data uses the same write circuitry as storing the analog data.
Claim 9
Dependent Claim
35 words
The method of claim 1 wherein a write circuit used to store samples of the analog signal in the memory cells is also used to store the digital data in the array of memory cells.
Claim 10
Dependent Claim
41 words
The method of claim 1 wherein storing the digital data comprises: converting the digital data into an analog representation of the digital data; altering a threshold voltage (VT) of a memory cell to hold the analog representation of the digital data.
Claim 11
Dependent Claim
20 words
The method of claim 9 wherein the analog representation of the digital data has more than two analog voltage levels.
Claim 12
Dependent Claim
27 words
The method of claim 1 further comprising the step of: writing every memory cell in a sector of the array of memory cells with a digital value.
Claim 13
Dependent Claim
20 words
The method of claim 11 wherein a source line of every memory cell in the selected sector is coupled together.
Claim 14
Dependent Claim
131 words
An integrated circuit comprising: an array of memory cells; a write circuit to store an information provided at an analog input and a digital input of the integrated circuit into the memory cells, wherein the information provided at the analog input is in an analog form and at the digital input is in digital form; and a multiplexer, coupled between the analog input and the write circuit, and the digital input and the write circuit, to selectively couple the analog input to the write circuit or the digital input to the write circuit, wherein the information provided at the analog input is sampled at a sampling frequency and each sample is stored in one memory cell, wherein the sampling frequency is user-selectable by providing a digital command to the integrated circuit.
Claim 15
Dependent Claim
131 words
An integrated circuit comprising: an array of memory cells; a write circuit to store an information provided at an analog input and a digital input of the integrated circuit into the memory cells, wherein the information provided at the analog input is in an analog form and at the digital input is in digital form; and a multiplexer, coupled between the analog input and the write circuit, and the digital input and the write circuit, to selectively couple the analog input to the write circuit or the digital input to the write circuit, wherein the information provided at the analog input is sampled at a sampling frequency and each sample is stored in one memory cell, wherein the sampling frequency is user-selectable by providing a digital command to the integrated circuit.
Claim 16
Dependent Claim
54 words
The integrated circuit of claim 13 further comprising: a register coupled to the digital input to hold the information in digital form; a converter circuit, coupled between the register and the multiplexer, receiving the information held in the register and generating an analog representation of the information suitable for storage in a memory cell.
Claim 17
Dependent Claim
16 words
The integrated circuit of claim 13 wherein the memory cells are analog or multilevel memory cells.
Claim 18
Dependent Claim
99 words
An integrated circuit comprising: a plurality of memory cells; a write circuit coupled to the memory cells; and a read circuit to determine a threshold voltage stored in individual memory cells, and to provide an analog equivalent of the stored threshold voltage at an analog output or to provide a digital equivalent of the stored threshold voltage at a digital output, wherein individual memory cells are configurable by the write circuit to store more than two different threshold voltage levels, and the read circuit provides a sequence of analog equivalents to the analog output at a user-selected playback frequency.
Claim 19
Dependent Claim
99 words
An integrated circuit comprising: a plurality of memory cells; a write circuit coupled to the memory cells; and a read circuit to determine a threshold voltage stored in individual memory cells, and to provide an analog equivalent of the stored threshold voltage at an analog output or to provide a digital equivalent of the stored threshold voltage at a digital output, wherein individual memory cells are configurable by the write circuit to store more than two different threshold voltage levels, and the read circuit provides a sequence of analog equivalents to the analog output at a user-selected playback frequency.
Claim 20
Dependent Claim
65 words
The integrated circuit of claim 16 wherein the read circuit determines whether a threshold voltage stored in a memory cell is above or below a reference level, and the read circuit provides to the digital output a first logic level when the stored threshold voltage is below the reference level and a second logic level when the stored threshold voltage is above the reference level.
Claim 21
Dependent Claim
28 words
The integrated circuit of claim 16 wherein the playback frequency is the sampling frequency used by the write circuit to store the analog signal in the memory cells.
Claim 22
Dependent Claim
16 words
The integrated circuit of claim 17 wherein the digital equivalent comprises more than one binary bit.
Claim 23
Dependent Claim
115 words
The integrated circuit of claim 14 wherein the converter circuit comprises: a bias voltage generator to generate a first and a second bias voltage; and a digital data input circuit coupled to the first and second bias voltages and the register, wherein when the information in the register is in a first state, the digital data input circuit outputs the first bias voltage on a first output line and the second bias voltage on a second output line, and when the information in the register is in a second state, the digital data input circuit outputs the second bias voltage on the first output line and the first bias voltage on the second output line.
Claim 24
Dependent Claim
63 words
The integrated circuit of claim 20 wherein the bias voltage generator comprises: a first and second transistor coupled between a first bias voltage output and a first supply line; a third transistor coupled between the first bias voltage output and a second bias voltage output; and a third and fourth transistor coupled between the second bias voltage output and a second supply line.
Claim 25
Dependent Claim
21 words
The integrated circuit of claim 21 wherein the third transistor has a lower threshold voltage than the third and fourth transistors.
Claim 26
Dependent Claim
14 words
The integrated circuit of claim 21 wherein the third transistor is a native device.
Claim 27
Dependent Claim
38 words
The integrated circuit of claim 20 wherein the converter circuit further comprises: a common mode feedback circuit coupled to the first and second output lines, generating a third bias voltage coupled to a gate of the fourth transistor.
Claim 28
Dependent Claim
92 words
An integrated circuit comprising: an array of multilevel memory cells; a write circuit coupled to store data in the array of multilevel memory cells; a digital reference generator, receiving digital data and converting the digital data into an analog equivalent form, wherein the analog equivalent form is provided to the write circuit, and the digital reference generator comprises: a bias voltage generator generating a plurality of bias voltages; and a digital data input circuit generating the analog equivalent form of the digital data by selecting combinations of the plurality of bias voltages.
Claim 29
Dependent Claim
92 words
An integrated circuit comprising: an array of multilevel memory cells; a write circuit coupled to store data in the array of multilevel memory cells; a digital reference generator, receiving digital data and converting the digital data into an analog equivalent form, wherein the analog equivalent form is provided to the write circuit, and the digital reference generator comprises: a bias voltage generator generating a plurality of bias voltages; and a digital data input circuit generating the analog equivalent form of the digital data by selecting combinations of the plurality of bias voltages.
Claim 30
Dependent Claim
35 words
The integrated circuit of claim 25 wherein the bias voltage generator comprises a plurality of impedances coupled in series, and a node between each of the impedances is coupled to the digital data input circuit.
Claim 31
Dependent Claim
17 words
The integrated circuit of claim 25 wherein the digital data input circuit provides a differential voltage output.
Claim 32
Dependent Claim
32 words
The integrated circuit of claim 27 wherein the digital reference generator further comprises: a common mode feedback circuit coupled to the differential voltage output and coupling back to the bias voltage generator.
Claim 33
Dependent Claim
84 words
An integrated circuit comprising a digital reference generator comprising: a first impedance coupled between a first supply line and a first output line; a second impedance coupled between the first output line and a first node; a third impedance coupled between the first node and a second output line; a fourth impedance coupled between the second output line and a second supply line; a first switch coupled in parallel with the second impedance; and a second switch coupled in parallel with the third impedance.
Claim 34
Dependent Claim
84 words
An integrated circuit comprising a digital reference generator comprising: a first impedance coupled between a first supply line and a first output line; a second impedance coupled between the first output line and a first node; a third impedance coupled between the first node and a second output line; a fourth impedance coupled between the second output line and a second supply line; a first switch coupled in parallel with the second impedance; and a second switch coupled in parallel with the third impedance.
Claim 35
Dependent Claim
15 words
The integrated circuit of claim 29 wherein the second and third impedances have different values.
Claim 36
Independent Claim
124 words
A method of storing information in a memory comprising: providing an analog signal at an analog signal input; providing digital data at a digital signal input; sampling the analog signal input at a sampling frequency; storing samples of the analog signal in an array of memory cells, wherein a memory cell holds at least one sample of the analog signal; and storing the digital data in the array of memory cells, wherein a memory cell holds at least a bit of the digital data, wherein storing the digital data comprises: erasing a sector of memory cells; writing the digital data in the sector of memory cells; and writing a digital value in each memory cell of the sector not written with the digital data.
Claim 37
Independent Claim
124 words
A method of storing information in a memory comprising: providing an analog signal at an analog signal input; providing digital data at a digital signal input; sampling the analog signal input at a sampling frequency; storing samples of the analog signal in an array of memory cells, wherein a memory cell holds at least one sample of the analog signal; and storing the digital data in the array of memory cells, wherein a memory cell holds at least a bit of the digital data, wherein storing the digital data comprises: erasing a sector of memory cells; writing the digital data in the sector of memory cells; and writing a digital value in each memory cell of the sector not written with the digital data.
Claim 38
Dependent Claim
18 words
The method of claim 31 wherein a memory cell holds at least two bits of the digital data.
Claim 39
Dependent Claim
26 words
The method of claim 31 wherein the digital data is clocked into and stored in the sector of memory cells serially in a first-in, first-out manner.
Claim 40
Dependent Claim
24 words
The method of claim 31 further comprising the step of: providing a command at the digital signal input to select a user-selected sampling frequency.
Claim 41
Dependent Claim
37 words
The method of claim 31 further comprising the step of: providing a write circuit to store samples of the analog signal in the memory cells and also store the digital data in the array of memory cells.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-03-26 | 2004-09-25 | 2005-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-03-26 | 2008-09-25 | 2009-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-03-26 | 2012-09-25 | 2013-03-27 | $7700.00 | Window Closed / Lapsed |