US5745409A
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US
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Non-volatile memory with analog and digital interface and storage
Assignee: SanDisk Technologies LLC
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Filing: 1995-09-28
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Granted: 1998-04-28
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Expires: 2015-09-28
Abstract
Abstract A non-volatile memory stores both analog and digital information in an array, and has digital and analog read and write circuits and dual I/O interfaces which allow input and output signals in digital or analog form. A user selects the input signal, output signal, and data storage formats. Each selection can be digital or analog format. On-chip analog-to-digital and digital-to-analog converters allow conversion of signals from one format into another. Analog signals can be read or written serially, and one embodiment includes an address counter and an internal oscillator for generating sequential addresses. An output amplifier for driving a speaker and an input amplifier for a microphone allow stored sounds to be directly recorded and reproduced.
Inventors
- 👤 Sau C. Wong
- 👤 Hock C. So
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:30
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/04; G01; G01R; G01R31/00; G01R31/28; G01R31/3167; G11C11/00; G11C11/56; G11C27/00; G11C27/005; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/20; G11C7/00; G11C7/16; G11C2211/00; G11C2211/56; G11C2211/564; G11C2211/5641; G11C2211/5644
Claims Analysis
Total Claims: 37
Claim 1
Independent Claim
77 words
An integrated memory comprising: an array of non-volatile memory cells; an analog write circuit coupled to the array, wherein the analog write circuit sets a threshold voltage of a memory cell to a level which depends on an analog signal; and a digital write circuit coupled to the array, wherein the digital write circuit sets a threshold voltage of a memory cell to a binary state which indicates a value of a bit in a digital signal.
Claim 2
Dependent Claim
77 words
An integrated memory comprising: an array of non-volatile memory cells; an analog write circuit coupled to the array, wherein the analog write circuit sets a threshold voltage of a memory cell to a level which depends on an analog signal; and a digital write circuit coupled to the array, wherein the digital write circuit sets a threshold voltage of a memory cell to a binary state which indicates a value of a bit in a digital signal.
Claim 3
Dependent Claim
55 words
The integrated memory of claim 1, further comprising: an analog input interface coupled to the analog write circuit and adapted to receive an analog signal to be stored in the array; and a digital input interface coupled to the digital write circuit and adapted to receive a digital signal to be stored in the array.
Claim 4
Dependent Claim
43 words
The integrated memory of claim 2, further comprising: an analog-to-digital converter coupled to the analog input interface; and a multiplexer having input ports coupled to the digital input interface and the analog-to-digital converter and an output port coupled to the digital write circuit.
Claim 5
Dependent Claim
44 words
The integrated memory of claim 2, further comprising: a digital-to-analog converter coupled to the digital input interface; and a first multiplexer having input ports coupled to the analog input interface and the digital-to-analog converter and an output port coupled to the analog write circuit.
Claim 6
Dependent Claim
44 words
The integrated memory of claim 4, further comprising: an analog-to-digital converter coupled to the analog input interface; and a second multiplexer having input ports coupled to the digital input interface and the analog-to-digital converter and an output port coupled to the digital write circuit.
Claim 7
Dependent Claim
81 words
The integrated memory of claim 5, further comprising: an analog read circuit coupled to the array, wherein the analog read circuit generates an analog output voltage which depends on a threshold voltage of a memory cell; and a digital read circuit coupled to the array, wherein the digital read circuit generates a digital signal containing one or more bits, each bit indicating whether a corresponding memory cell has a threshold voltage in a first binary state or a second binary state.
Claim 8
Dependent Claim
45 words
The integrated memory of claim 6, further comprising: a second digital-to-analog converter coupled to the digital read circuit; and a third multiplexer having input ports coupled to the analog read circuit and the second digital-to-analog converter, and an output port which provides an analog signal.
Claim 9
Dependent Claim
46 words
The integrated memory of claim 7, further comprising: a second analog-to-digital converter coupled to the analog read circuit; and a fourth multiplexer having input ports coupled to the digital read circuit and the second analog-to-digital converter, and an output port which provides a multi-bit digital signal.
Claim 10
Dependent Claim
46 words
The integrated memory of claim 6, further comprising: a second analog-to-digital converter coupled to the analog read circuit; and a third multiplexer having input ports coupled to the digital read circuit and the second analog-to-digital converter, and an output port which provides a multi-bit digital signal.
Claim 11
Dependent Claim
81 words
The integrated memory of claim 2, further comprising: an analog read circuit coupled to the array, wherein the analog read circuit generates an analog output voltage which depends on a threshold voltage of a memory cell; and a digital read circuit coupled to the array, wherein the digital read circuit generates a digital signal containing a plurality of bits, each bit indicating whether a corresponding memory cell has a threshold voltage in a first binary state or a second binary state.
Claim 12
Dependent Claim
90 words
The integrated memory of claim 10, further comprising: an analog-to-digital converter; a first multiplexer having input ports coupled to the digital input interface and the analog-to-digital converter and an output port coupled to the digital write circuit; a second multiplexer having input terminals coupled to the analog read circuit and the analog input interface and an output terminal coupled to the analog-to-digital converter; and a third multiplexer having input ports coupled to the analog-to-digital converter and to digital read circuit and an output port which provides a multi-bit digital signal.
Claim 13
Dependent Claim
89 words
The integrated memory of claim 10, further comprising: a digital-to-analog converter; a first multiplexer having input terminals coupled to the analog input interface and the digital-to-analog converter and an output terminal coupled to the analog write circuit; a second multiplexer having input ports coupled to the digital read circuit and the digital input interface and an output port coupled to the digital-to-analog converter; and a third multiplexer having input terminals coupled to the digital-to-analog converter and to analog read circuit and an output terminal which provides an analog signal.
Claim 14
Dependent Claim
90 words
The integrated memory of claim 12, further comprising: an analog-to-digital converter; a fourth multiplexer having input ports coupled to the digital input interface and the analog-to-digital converter and an output port coupled to the digital write circuit; a fifth multiplexer having input terminals coupled to the analog read circuit and the analog input interface and an output terminal coupled to the analog-to-digital converter; and a sixth multiplexer having input ports coupled to the analog-to-digital converter and to digital read circuit and an output port which provides a multi-bit digital signal.
Claim 15
Dependent Claim
81 words
The integrated memory of claim 1, further comprising: an analog read circuit coupled to the array, wherein the analog read circuit generates an analog output voltage which depends on a threshold voltage of a memory cell; and a digital read circuit coupled to the array, wherein the digital read circuit generates a digital signal containing a plurality of bits, each bit indicating whether a corresponding memory cell has a threshold voltage in a first binary state or a second binary state.
Claim 16
Dependent Claim
44 words
The integrated memory of claim 14, further comprising: an analog-to-digital converter coupled to the analog read circuit; and a first multiplexer having input ports coupled to the digital read circuit and the analog-to-digital converter, and an output port which provides a multi-bit digital signal.
Claim 17
Dependent Claim
62 words
The integrated memory of claim 15, further comprising: an analog input interface; a digital input interface coupled to the digital write circuit; a digital-to-analog converter coupled to the digital input interface; and a second multiplexer having input terminals coupled to the analog input interface and the digital-to-analog converter, and an output terminal which provides an analog signal to the analog write circuit.
Claim 18
Dependent Claim
43 words
The integrated memory of claim 14, further comprising: a digital-to-analog converter coupled to the digital read circuit; and a first multiplexer having input ports coupled to the analog read circuit and the digital-to-analog converter, and an output port which provides an analog signal.
Claim 19
Dependent Claim
62 words
The integrated memory of claim 17, further comprising: an analog input interface coupled to the analog write circuit; a digital input interface; an analog-to-digital converter coupled to the analog input interface; and a second multiplexer having input ports coupled to the digital input interface and the analog-to-digital converter, and an output port which provides a digital signal to the digital write circuit.
Claim 20
Dependent Claim
44 words
The integrated memory of claim 17, further comprising: an analog-to-digital converter coupled to the analog read circuit; and a second multiplexer having input ports coupled to the digital read circuit and the analog-to-digital converter, and an output port which provides a multi-bit digital signal.
Claim 21
Dependent Claim
65 words
The integrated memory of claim 1, further comprising a counter coupled to the memory array and adapted to store an address for the memory array, wherein: in response to a clock signal asserted to the counter, the counter increments the address; and the analog write circuit sets the threshold voltage of a memory cell in the memory array, at the address stored in the counter.
Claim 22
Dependent Claim
70 words
The integrated memory of claim 20, further comprising: an address port adapted to receive a signal indicating an address of a memory cell in the memory array, wherein the counter is coupled to the address port and adapted to load an address from the address port; and a multiplexer having input ports coupled to the address port and to the counter and an output port coupled to the memory array.
Claim 23
Dependent Claim
26 words
The integrated memory of claim 21, further comprising an oscillator coupled to the counter and the analog write circuit, wherein the oscillator generates the clock signal.
Claim 24
Dependent Claim
26 words
The integrated memory of claim 20, further comprising an oscillator coupled to the counter and the analog write circuit, wherein the oscillator generates the clock signal.
Claim 25
Dependent Claim
45 words
The integrated memory of claim 1, wherein the array is partitioned into a plurality of sections and each section comprises a non-volatile memory cell dedicated for storing a flag value which indicates whether memory cells in the section are for storing binary or analog values.
Claim 26
Dependent Claim
22 words
The integrated memory of claim 24, wherein the memory cells dedicated for storing the flag values form a column in the array.
Claim 27
Dependent Claim
33 words
The integrated memory of claim 1, wherein the digital write circuit simultaneously sets threshold voltages of a plurality of memory cells to binary states which indicate the value of the multi-bit digital signal.
Claim 28
Dependent Claim
172 words
An integrated memory comprising: an array of non-volatile memory cells; an analog input interface adapted to receive an analog signal; an analog write circuit coupled to the array and the analog input interface, wherein the analog write circuit sets a threshold voltage of a memory cell to indicate a level of the analog signal; a counter coupled to the memory array and adapted to store an address for the memory array, wherein in response to a clock signal asserted to the counter, the counter increments the address and the analog write circuit sets the threshold voltage of a memory cell in the memory array, at the address in the counter; an address port adapted to receive a signal indicating an address of a memory cell in the memory array, wherein the counter is coupled to the address port and adapted to load an address from the address port; and a multiplexer having input ports coupled to the address port and to the counter and an output port coupled to the memory array.
Claim 29
Dependent Claim
172 words
An integrated memory comprising: an array of non-volatile memory cells; an analog input interface adapted to receive an analog signal; an analog write circuit coupled to the array and the analog input interface, wherein the analog write circuit sets a threshold voltage of a memory cell to indicate a level of the analog signal; a counter coupled to the memory array and adapted to store an address for the memory array, wherein in response to a clock signal asserted to the counter, the counter increments the address and the analog write circuit sets the threshold voltage of a memory cell in the memory array, at the address in the counter; an address port adapted to receive a signal indicating an address of a memory cell in the memory array, wherein the counter is coupled to the address port and adapted to load an address from the address port; and a multiplexer having input ports coupled to the address port and to the counter and an output port coupled to the memory array.
Claim 30
Dependent Claim
26 words
The integrated memory of claim 27, further comprising an oscillator coupled to the counter and the analog write circuit, wherein the oscillator generates the clock signal.
Claim 31
Dependent Claim
129 words
An integrated memory comprising: an array of non-volatile memory cells; an analog input interface adapted to receive an analog signal; an analog write circuit coupled to the array and the analog input interface, wherein the analog write circuit sets a threshold voltage of a memory cell to indicate a level of the analog signal; a counter coupled to the memory array and adapted to store an address for the memory array, wherein in response to a clock signal asserted to the counter, the counter increments the address and the analog write circuit sets the threshold voltage of a memory cell in the memory array, at the address in the counter; and an oscillator coupled to the counter and the analog write circuit, wherein the oscillator generates the clock signal.
Claim 32
Dependent Claim
129 words
An integrated memory comprising: an array of non-volatile memory cells; an analog input interface adapted to receive an analog signal; an analog write circuit coupled to the array and the analog input interface, wherein the analog write circuit sets a threshold voltage of a memory cell to indicate a level of the analog signal; a counter coupled to the memory array and adapted to store an address for the memory array, wherein in response to a clock signal asserted to the counter, the counter increments the address and the analog write circuit sets the threshold voltage of a memory cell in the memory array, at the address in the counter; and an oscillator coupled to the counter and the analog write circuit, wherein the oscillator generates the clock signal.
Claim 33
Dependent Claim
160 words
An integrated memory comprising: an array of non-volatile memory cells; an analog read circuit coupled to the array, wherein the analog read circuit reads a threshold voltage of a memory cell and generates an analog output signal indicating the threshold voltage; and a counter coupled to the memory array and adapted to store an address for the memory array, wherein in response to a clock signal asserted to the counter, the counter increments the address and the analog read circuit reads the threshold voltage of a memory cell in the memory array, at the address in the counter; an address port adapted to receive a signal indicating an address of a memory cell in the memory array, wherein the counter is coupled to the address port and adapted to load an address from the address port; and a multiplexer having input ports coupled to the address port and to the counter and an output port coupled to the memory array.
Claim 34
Dependent Claim
160 words
An integrated memory comprising: an array of non-volatile memory cells; an analog read circuit coupled to the array, wherein the analog read circuit reads a threshold voltage of a memory cell and generates an analog output signal indicating the threshold voltage; and a counter coupled to the memory array and adapted to store an address for the memory array, wherein in response to a clock signal asserted to the counter, the counter increments the address and the analog read circuit reads the threshold voltage of a memory cell in the memory array, at the address in the counter; an address port adapted to receive a signal indicating an address of a memory cell in the memory array, wherein the counter is coupled to the address port and adapted to load an address from the address port; and a multiplexer having input ports coupled to the address port and to the counter and an output port coupled to the memory array.
Claim 35
Dependent Claim
26 words
The integrated memory of claim 30, further comprising an oscillator coupled to the counter and the analog read circuit, wherein the oscillator generates the clock signal.
Claim 36
Dependent Claim
117 words
An integrated memory comprising: an array of non-volatile memory cells; an analog read circuit coupled to the array, wherein the analog read circuit reads a threshold voltage of a memory cell and generates an analog output signal indicating the threshold voltage; and a counter coupled to the memory array and adapted to store an address for the memory array, wherein in response to a clock signal asserted to the counter, the counter increments the address and the analog read circuit reads the threshold voltage of a memory cell in the memory array, at the address in the counter; and an oscillator coupled to the counter and the analog write circuit, wherein the oscillator generates the clock signal.
Claim 37
Dependent Claim
117 words
An integrated memory comprising: an array of non-volatile memory cells; an analog read circuit coupled to the array, wherein the analog read circuit reads a threshold voltage of a memory cell and generates an analog output signal indicating the threshold voltage; and a counter coupled to the memory array and adapted to store an address for the memory array, wherein in response to a clock signal asserted to the counter, the counter increments the address and the analog read circuit reads the threshold voltage of a memory cell in the memory array, at the address in the counter; and an oscillator coupled to the counter and the analog write circuit, wherein the oscillator generates the clock signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-04-27 | 2001-10-27 | 2002-04-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-04-27 | 2005-10-27 | 2006-04-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-04-27 | 2009-10-27 | 2010-04-28 | $7700.00 | Window Closed / Lapsed |