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US6208030B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device having a low dielectric constant material

Assignee: GlobalFoundries Inc
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Filing: 1998-10-27
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Granted: 2001-03-27
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Expires: 2018-10-27
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Abstract

Abstract A semiconductor device having a reduced resistance-capacitance time constant is formed by treating a dielectric layer to reduce its dielectric constant. Embodiments include exposing a deposited dielectric layer to ionic radiation, as with Helium ion implantation, to form voids within the layer, thereby reducing its dielectric constant.

Inventors

  • 👤 Ting Y. Tsui
  • 👤 Ercan Adem

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 01:56
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/45; H10W20/48; H10W20/495

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 104 words
A semiconductor device comprising: a first conductive layer; a dielectric layer having a dielectric constant on the first conductive layer; and a second conductive layer on the dielectric layer, wherein the dielectric layer contains voids having a diameter of about 100 Å to about 1,000 Å substantially throughout the dielectric layer, thereby lowering the dielectric constant of the dielectric layer, wherein the dielectric layer comprises a silicon oxide layer, wherein the silicon oxide layer contains implanted atoms selected from the group consisting of helium, neon, argon, krypton, xenon, deuterium and hydrogen ions, and wherein the silicon oxide layer has a porosity of about 15%.
Claim 2
Dependent Claim 104 words
A semiconductor device comprising: a first conductive layer; a dielectric layer having a dielectric constant on the first conductive layer; and a second conductive layer on the dielectric layer, wherein the dielectric layer contains voids having a diameter of about 100 Å to about 1,000 Å substantially throughout the dielectric layer, thereby lowering the dielectric constant of the dielectric layer, wherein the dielectric layer comprises a silicon oxide layer, wherein the silicon oxide layer contains implanted atoms selected from the group consisting of helium, neon, argon, krypton, xenon, deuterium and hydrogen ions, and wherein the silicon oxide layer has a porosity of about 15%.
Claim 3
Dependent Claim 21 words
The semiconductor device of claim 1 , wherein the dielectric constant of the dielectric layer is no greater than about 3.9.
Claim 4
Dependent Claim 26 words
The semiconductor device of claim 1 , wherein the first conductive layer is over a single crystal silicon substrate having at least one active device region.
Claim 5
Dependent Claim 40 words
The semiconductor device of claim 1 , wherein the first conductive layer comprises a metal, the dielectric layer is directly on the first conductive layer and the second conductive layer comprises a metal and is directly on the dielectric layer.

References Cited (Backward Citations)

US4001049A Cited
US5780919A Cited
US5393712A Cited
US5598026A Cited
US5892269A Cited
US6008540A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-03-26 2004-09-25 2005-03-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2008-03-26 2008-09-25 2009-03-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2012-03-26 2012-09-25 2013-03-27 $7700.00 Window Closed / Lapsed

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