Semiconductor device with ohmic contacts on compound semiconductor and manufacture thereof

Claim 2

A semiconductor device comprising: a substrate having a first surface layer in a surface area, the first surface layer being made of a compound semiconductor material; a first intermediate layer formed on the first surface layer, made of a compound material containing Ga as a group III element and S as a group VI element, and having a thickness of at least two monolayers or thicker; and a first electrode formed on the first intermediate layer, the first electrode being electrically connected to the first surface layer with an ohmic contact.

Claim 3

A semiconductor device according to claim 1 , wherein the first intermediate layer is made of GaS.

Claim 4

A semiconductor device according to claim 1 , wherein the first surface layer and the first intermediate layer are of a same conductivity type.

Claim 5

A semiconductor device according to claim 1 , wherein the first surface layer is made of one of materials selected from a group consisting of GaAs, AlGaAs, InGaP, InP, InGaAs, InAlAs, InAlGaAs, GaN, AlGaN, InGaN, InAlN, InN, AlN, InAlGaN, InGaAsN, InAlAsN and InAlGaAsN.

Claim 6

A semiconductor device according to claim 1 , wherein a thickness of the first intermediate layer is 5 to 20 nm.

Claim 7

A semiconductor device according to claim 1 , further comprising: a second surface layer disposed in another surface area spaced apart from the first surface layer by a certain distance, the second surface layer being made of a same compound semiconductor material as the first surface layer; a second intermediate layer formed on the second surface layer, made of a same compound material as the first intermediate layer, and having a thickness of at least two monolayers or thicker; a second electrode formed on the second intermediate layer, the second electrode being electrically connected to the second surface layer with an ohmic contact; a channel layer disposed in an area between the first and second surface layers, coupled to the first and second surface layers, and made of a compound semiconductor material; and a gate electrode formed on the channel layer and electrically connected to the channel layer with a Schottky contact.

Claim 8

A semiconductor device according to claim 6 , wherein the first intermediate layer covers surfaces of the first surface layer and the channel layer between the first electrode and the gate electrode, and the second intermediate layer covers surfaces of the second surface layer and the channel layer between the second electrode and the gate electrode.

Claim 9

A semiconductor device according to claim 1 , wherein the substrate comprises: a support substrate having a principal surface; a channel layer formed on the principal surface of the support substrate and made of a non-doped compound semiconductor material; and a carrier supply layer formed on the channel layer, having a band gap larger than a band gap of the channel layer, and made of a compound semiconductor material doped with conductive impurities, wherein the first surface layer is formed on the carrier supply layer in a surface area thereof, and wherein the semiconductor device further comprises: a second surface layer disposed in another surface area of the carrier supply layer spaced apart from the first surface layer by a certain distance, the second surface layer being made of a same compound semiconductor material as the first surface layer; a second intermediate layer formed on the second surface layer, made of a same compound material as the first intermediate layer, and having a thickness of at least two monolayers or thicker; a second electrode formed on the second intermediate layer, the second electrode being electrically connected to the second surface layer with an ohmic contact; and a gate electrode electrically connected to the carrier supply layer with a Schottky contact at the area between the first surface layer and the second surface layer.

Claim 10

A semiconductor device according to claim 8 , wherein the first intermediate layer covers surfaces of the first surface layer and the carrier supply layer between the first electrode and the gate electrode, and the second intermediate layer covers surfaces of the second surface layer and the carrier supply layer between the second electrode and the gate electrode.

Claim 11

A semiconductor device according to claim 1 , further comprising: a second electrode formed on a surface of the first intermediate layer where the first electrode is not formed, the second electrode being disposed spaced apart from the first electrode by a certain distance and electrically connected to the second electrode with an ohmic contact; an insulating layer formed on a surface of the first intermediate layer between the first and second electrodes; and a gate electrode formed on the insulating layer.

Claim 12

A semiconductor device comprising: a substrate having a principal surface; a collector layer formed on the principal surface of the substrate and made of a compound semiconductor material of a first conductivity type; a base layer formed on a partial surface area of the collector layer and made of a compound semiconductor material of a second conductivity type opposite to the first conductivity type; an emitter layer formed on a partial surface area of the base layer and made of a compound semiconductor material of the first conductivity type; a collector electrode formed on a surface of the collector layer where the base layer is not formed, the collector electrode being electrically connected to the collector layer with an ohmic contact; a base electrode formed on a surface of the base layer where the emitter layer is not formed, the base electrode being electrically connected to the base layer with an ohmic contact; an emitter electrode formed on a surface of the emitter layer and electrically connected to the emitter layer with an ohmic contact; and an intermediate layer disposed at least one area between the collector electrode and the collector layer, between the base electrode and the base layer, or between the emitter electrode and the emitter layer, the intermediate layer being made of a compound material containing Ga as a III group III element and S as a VI group VI element and having a thickness of at least two monolayers or thicker.

Claim 13

A semiconductor device comprising: a substrate having a principal surface; a collector layer formed on the principal surface of the substrate and made of a compound semiconductor material of a first conductivity type; a base layer formed on a partial surface area of the collector layer and made of a compound semiconductor material of a second conductivity type opposite to the first conductivity type; an emitter layer formed on a partial surface area of the base layer and made of a compound semiconductor material of the first conductivity type; a collector electrode formed on a surface of the collector layer where the base layer is not formed, the collector electrode being electrically connected to the collector layer with an ohmic contact; a base electrode formed on a surface of the base layer where the emitter layer is not formed, the base electrode being electrically connected to the base layer with an ohmic contact; an emitter electrode formed on a surface of the emitter layer and electrically connected to the emitter layer with an ohmic contact; and an intermediate layer disposed at least one area between the collector electrode and the collector layer, between the base electrode and the base layer, or between the emitter electrode and the emitter layer, the intermediate layer being made of a compound material containing Ga as a III group III element and S as a VI group VI element and having a thickness of at least two monolayers or thicker.

Claim 14

A semiconductor device according to claim 11 , wherein the intermediate layer is disposed between the base electrode and the base layer and covers a surface area of the base layer between the base electrode and the emitter layer.

Claim 15

A semiconductor device comprising: a substrate having a surface layer made of a compound semiconductor material; a source electrode and a drain electrode directly formed on the surface layer of the substrate and spaced apart by a certain distance in an in-plane of the surface layer; a gate electrode formed on a surface area of the surface layer between the source electrode and the drain electrode and spaced apart from the source electrode and the drain electrode by a certain distance; and a GaS compound layer covering surface areas of the surface layer of the substrate between the gate electrode and the drain electrode and between the source electrode and the drain electrode and having a thickness of at least two monolayers or thicker.

Claim 16

A semiconductor device comprising: a substrate having a surface layer made of a compound semiconductor material; a source electrode and a drain electrode directly formed on the surface layer of the substrate and spaced apart by a certain distance in an in-plane of the surface layer; a gate electrode formed on a surface area of the surface layer between the source electrode and the drain electrode and spaced apart from the source electrode and the drain electrode by a certain distance; and a GaS compound layer covering surface areas of the surface layer of the substrate between the gate electrode and the drain electrode and between the source electrode and the drain electrode and having a thickness of at least two monolayers or thicker.

Claim 17

A semiconductor device according to claim 13 , wherein a substantial composition ratio of Ga and S of the GaS compound layer is 1:1.

Claim 18

A semiconductor device according to claim 13 , wherein a thickness of the GaS compound layer is 3 nm or thicker.

Claim 19

A semiconductor device according to claim 13 , wherein the GaS compound layer is also inserted between the surface layer of the substrate and the gate electrode.

Claim 20

A semiconductor device according to claim 13 , wherein the gate electrode is in direct contact with the surface layer of the substrate, the semiconductor device further comprises: another source electrode and another drain electrode directly formed on the surface layer of the substrate and spaced apart by a certain distance in an in-plane of the surface layer; another gate electrode directly formed on a surface area of the surface layer between the other source electrode and the other drain electrode and spaced apart from the other source electrode and the other drain electrode by a certain distance; and another GaS compound layer covering surface areas of the surface layer of the substrate between the other gate electrode and the other source electrode and between the other gate electrode and the other drain electrode and having a thickness of at least two monolayers or thicker, and an impurity concentration of a region of the surface layer of the substrate under the gate electrode is different from an impurity concentration of a region of the surface layer of the substrate under the other gate electrode.

Claim 21

A semiconductor device according to claim 13 , wherein the surface layer of the substrate comprises a channel layer made of a non-doped compound semiconductor material, a carrier supply layer doped with conductive impurities, and a cap layer made of a compound semiconductor material of a same conductivity type as the carrier supply layer, respectively stacked in this order from a bottom layer, a groove is formed in a region of the surface layer between the source electrode and the drain electrode, tile groove having a depth not reaching the channel layer, and the gate electrode is formed on a bottom of the groove.

Claim 22

A semiconductor device according to claim 13 , further comprising: another source electrode and another drain electrode directly formed on the surface layer of the substrate and spaced apart by a certain distance in an in-plane of the surface layer; another groove formed in a region of the surface layer between the other source electrode and the other drain electrode, the other groove having a depth not reaching the channel layer arid different from the groove; another gate electrode formed on a bottom of the other groove and spaced apart by a certain distance from the other source electrode and the other drain electrode; and another GaS compound layer covering surface areas of the surface layer of the substrate between the other gate electrode and the other source electrode and between the gate electrode and the other drain electrode and having a thickness of at least two monolayers or thicker.

Claim 23

A semiconductor device according to claim 19 , wherein the cap layer comprises two layers made of materials having different etching resistances, an interface between the two layers being set to a certain depth, the groove has the bottom at a level deeper than the interface, and the interface is exposed on the bottom of the other groove.

Claim 24

A semiconductor device comprising: a III-V group III-V compound semiconductor layer: an ohmic contact layer formed on the III-V group compound semiconductor layer, the ohmic contact layer containing at least Ti, and S, Se or Te; and a metal layer formed on the ohmic contact layer.

Claim 25

A semiconductor device comprising: a III-V group III-V compound semiconductor layer: an ohmic contact layer formed on the III-V group compound semiconductor layer, the ohmic contact layer containing at least Ti, and S, Se or Te; and a metal layer formed on the ohmic contact layer.

Claim 26

A semiconductor device comprising: a channel layer formed on a semiconductor substrate; an electron supply layer formed on the channel layer; a contact layer formed on the electron supply layer and made of a III-V group III-V compound semiconductor material; an ohmic contact layer formed on the contact layer, the ohmic contacts layer containing at least Ti, and S, Se or Te; a source electrode and a drain electrode formed on the ohmic contact layer; and a gate electrode formed on the electron supply layer between the source electrode and the drain electrode.

Claim 27

A semiconductor device comprising: a channel layer formed on a semiconductor substrate; an electron supply layer formed on the channel layer; a contact layer formed on the electron supply layer and made of a III-V group III-V compound semiconductor material; an ohmic contact layer formed on the contact layer, the ohmic contacts layer containing at least Ti, and S, Se or Te; a source electrode and a drain electrode formed on the ohmic contact layer; and a gate electrode formed on the electron supply layer between the source electrode and the drain electrode.