US6189070B1
Expired / Lapsed
US
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Apparatus and method for suspending operation to read code in a nonvolatile writable semiconductor memory
Assignee: Intel Corp
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Filing: 1997-08-28
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Granted: 2001-02-13
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Expires: 2017-08-28
Abstract
Abstract A method and apparatus manages data and reads code from a nonvolatile writeable memory. In a nonvolatile writeable system, interrupts are disabled. A non-read operation is initiated in the nonvolatile writeable memory. A check for whether an interrupt has occurred is performed. If an interrupt has occurred, then the non-read operation in the nonvolatile writeable memory is suspended. Interrupts are enabled, and code is read from the nonvolatile writeable memory. Non-read operations may include program operations and erase operations.
Inventors
- 👤 Deborah L. See
- 👤 Robert N. Hasbun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 13:47
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/10; G11C2216/00; G11C2216/12; G11C2216/20
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
98 words
A method of reading code from a nonvolatile writeable memory having at least a read mode and a write mode of operation, comprising: (a) disabling interrupts; (b) initiating a non-read operation in the memory, wherein the memory is operated in the write mode and, wherein, the non-read operation is initiated by low-level routines downloaded to a volatile memory from the memory; and (c) checking for interrupts, and in response to detecting an interrupt performing: (i) suspending the non-read operation, wherein the memory is operated in the read mode; (ii) enabling interrupts; and (iii) reading code from the memory.
Claim 2
Independent Claim
98 words
A method of reading code from a nonvolatile writeable memory having at least a read mode and a write mode of operation, comprising: (a) disabling interrupts; (b) initiating a non-read operation in the memory, wherein the memory is operated in the write mode and, wherein, the non-read operation is initiated by low-level routines downloaded to a volatile memory from the memory; and (c) checking for interrupts, and in response to detecting an interrupt performing: (i) suspending the non-read operation, wherein the memory is operated in the read mode; (ii) enabling interrupts; and (iii) reading code from the memory.
Claim 3
Dependent Claim
22 words
The method of claim 1 , wherein disabling interrupts further comprises disabling task switches and enabling interrupts further comprises enabling task switches.
Claim 4
Dependent Claim
21 words
The method of claim 1 wherein initiating a non-read operation is performed by initiating a non-read operation in a flash memory.
Claim 5
Dependent Claim
31 words
The method of claim 1 , wherein disabling interrupts is performed by writing to a register within a processor to disable the processor from automatically handling an interrupt when it occurs.
Claim 6
Dependent Claim
27 words
The method of claim 1 , wherein initiating a non-read operation in the nonvolatile writeable memory is initiated within a data section of the nonvolatile writeable memory.
Claim 7
Independent Claim
137 words
A system comprising: a processor; a nonvolatile writeable memory having an array, the nonvolatile writeable memory having a first mode for allowing the array to be written to, and a second mode for allowing the array to be read from, the nonvolatile writeable memory storing low level code which when executed by the processor cause the processor to perform: (a) disabling interrupts; (b) initiating a non-read operation to the nonvolatile writeable memory while the array is in the first mode and, wherein, the non-read operation is initiated by low-level routines downloaded to a volatile memory from the nonvolatile writeable memory; (c) checking for interrupts, and in response to detecting an interrupt performing: (i) suspending the non-read operation; (ii) placing the array in the second mode; (iii) enabling interrupts; and (iv) reading code from the nonvolatile writeable memory.
Claim 8
Independent Claim
137 words
A system comprising: a processor; a nonvolatile writeable memory having an array, the nonvolatile writeable memory having a first mode for allowing the array to be written to, and a second mode for allowing the array to be read from, the nonvolatile writeable memory storing low level code which when executed by the processor cause the processor to perform: (a) disabling interrupts; (b) initiating a non-read operation to the nonvolatile writeable memory while the array is in the first mode and, wherein, the non-read operation is initiated by low-level routines downloaded to a volatile memory from the nonvolatile writeable memory; (c) checking for interrupts, and in response to detecting an interrupt performing: (i) suspending the non-read operation; (ii) placing the array in the second mode; (iii) enabling interrupts; and (iv) reading code from the nonvolatile writeable memory.
Claim 9
Dependent Claim
22 words
The system of claim 6 wherein the entire array alternates from being in the first mode to being in the second mode.
Claim 10
Dependent Claim
25 words
The system of claim 6 further comprising a second memory that actually stores a copy of the low level code of the nonvolatile writeable memory.
Claim 11
Dependent Claim
17 words
The system of claim 6 wherein initiating a non-read operation is performed by initiating a program operation.
Claim 12
Dependent Claim
36 words
The system of claim 6 wherein the low level code, when executed by the processor, causes the processor to further perform, in response to detecting the interrupt: (v) executing the code read during the step (iv).
Claim 13
Dependent Claim
102 words
A computer-readable medium having stored thereon a plurality of instructions which, when executed by a processor, cause the processor to perform: (a) disabling interrupts; (b) initiating a non-read operation to the nonvolatile writeable memory while the array is in a first mode and, wherein, the non-read operation is initiated by low-level routines downloaded to a volatile memory from the nonvolatile writeable memory; (c) checking for interrupts, and in response to detecting an interrupt performing the steps of: (i) suspending the non-read operation; (ii) placing the array in a second mode; (iii) enabling interrupts; and (iv) reading code from the nonvolatile writeable memory.
Claim 14
Dependent Claim
102 words
A computer-readable medium having stored thereon a plurality of instructions which, when executed by a processor, cause the processor to perform: (a) disabling interrupts; (b) initiating a non-read operation to the nonvolatile writeable memory while the array is in a first mode and, wherein, the non-read operation is initiated by low-level routines downloaded to a volatile memory from the nonvolatile writeable memory; (c) checking for interrupts, and in response to detecting an interrupt performing the steps of: (i) suspending the non-read operation; (ii) placing the array in a second mode; (iii) enabling interrupts; and (iv) reading code from the nonvolatile writeable memory.
Claim 15
Dependent Claim
36 words
The computer-readable medium of claim 11 , wherein said plurality of instructions, when executed by a processor, cause said processor to perform: (d) disabling task switching concurrent with at least a portion of (a) to (c).
Claim 16
Independent Claim
119 words
A method of reading code from a first nonvolatile writeable memory block while managing data in a second block nonvolatile writeable memory block, the method comprising: (a) disabling interrupts; (b) initiating a non-read operation in the second nonvolatile writeable memory block, wherein the second nonvolatile writeable memory is operated in a write mode and, wherein, the non-read operation is initiated by low-level routines downloaded to a volatile memory block from the nonvolatile writeable memory block; and (c) checking for interrupts, and in response to detecting an interrupt performing: (i) suspending the non-read operation, wherein the second nonvolatile writeable memory is operated in a read mode; (ii) enabling interrupts; and (iii) reading code from the first nonvolatile writeable memory block.
Claim 17
Independent Claim
119 words
A method of reading code from a first nonvolatile writeable memory block while managing data in a second block nonvolatile writeable memory block, the method comprising: (a) disabling interrupts; (b) initiating a non-read operation in the second nonvolatile writeable memory block, wherein the second nonvolatile writeable memory is operated in a write mode and, wherein, the non-read operation is initiated by low-level routines downloaded to a volatile memory block from the nonvolatile writeable memory block; and (c) checking for interrupts, and in response to detecting an interrupt performing: (i) suspending the non-read operation, wherein the second nonvolatile writeable memory is operated in a read mode; (ii) enabling interrupts; and (iii) reading code from the first nonvolatile writeable memory block.
References Cited (Backward Citations)
US5021996A
Cited
US5287469A
Cited
US4965828A
Cited
US5418752A
Cited
US5414829A
Cited
US5355464A
Cited
US5377145A
Cited
US5255314A
Cited
US5422843A
Cited
US5351216A
Cited
US5369754A
Cited
US5424992A
Cited
US5424993A
Cited
US5590073A
Cited
US5521864A
Cited
US5742787A
Cited
US5568644A
Cited
US5805929A
Cited
US5687121A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-02-13 | 2004-08-14 | 2005-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-02-13 | 2008-08-14 | 2009-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-02-13 | 2012-08-14 | 2013-02-13 | $7700.00 | Window Closed / Lapsed |