US5414829A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Override timing control circuitry and method for terminating program and erase sequences in a flash memory
Assignee: Intel Corp
•
Filing: 1993-09-10
•
Granted: 1995-05-09
•
Expires: 2013-09-10
Abstract
Abstract Override control circuitry and a method for terminating a sequence for erasing or programming a computer memory are described. A command register is provided for storing a command sent by an external processor to the memory. A decoder circuit decodes the command and outputs an erase or program set-up signal if the command indicates the initiation of an erase or program sequence. A latch is coupled to the decode circuit for storing the erase or program set-up signal. An override timer is located between the latch and the memory. The override timer includes a counter which is initialized and begins counting when the erase or program set-up signal is latched. The override timer also includes a circuit that detects when the counter has reached a first count for an erase sequence and a second count for a program sequence. The circuit then generates an erase or program override signal. An erase switch detects the erase override signal and prevents the application of an erase voltage to the memory. A program switch detects the program override signal and prevents the application of a program voltage to the memory. A voltage detector is also provided to terminate the erase or program sequences when the erase voltage or program voltage falls below a selected voltage level.
Inventors
- 👤 Mickey L. Fandrich
- 👤 Owen W. Jungroth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:51
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14; G11C16/16; G11C16/32
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
190 words
Override timing control circuitry for overriding a memory erase sequence controlled by an external processor, the override timing control circuitry residing on a same substrate as a memory, the memory including a plurality of data pins, the override timing control circuitry comprising: (a) a command register for storing a command sent by the processor to the memory via the plurality of data pins; (b) decode circuitry coupled to the command register for decoding the command, the decode circuitry outputting a first value if the command represents a call to initiate the memory erase sequence; (c) a first latch coupled to the decode circuitry for storing the first value; (d) an override timer coupled between the first latch and the memory, comprising: (1) a counter that is initialized and begins counting when the first value is stored in the first latch; and (2) circuitry responsive to the counter for generating an override signal for terminating the memory erase sequence when the counter reaches a first count; and (e) an erase switch for controlling the application of an erase voltage to the memory, the erase switch being responsive to the override signal.
Claim 2
Dependent Claim
190 words
Override timing control circuitry for overriding a memory erase sequence controlled by an external processor, the override timing control circuitry residing on a same substrate as a memory, the memory including a plurality of data pins, the override timing control circuitry comprising: (a) a command register for storing a command sent by the processor to the memory via the plurality of data pins; (b) decode circuitry coupled to the command register for decoding the command, the decode circuitry outputting a first value if the command represents a call to initiate the memory erase sequence; (c) a first latch coupled to the decode circuitry for storing the first value; (d) an override timer coupled between the first latch and the memory, comprising: (1) a counter that is initialized and begins counting when the first value is stored in the first latch; and (2) circuitry responsive to the counter for generating an override signal for terminating the memory erase sequence when the counter reaches a first count; and (e) an erase switch for controlling the application of an erase voltage to the memory, the erase switch being responsive to the override signal.
Claim 3
Dependent Claim
41 words
The override timing control circuitry of claim 1, wherein: (a) the counter comprises a plurality of flip-flops; and (b) the circuitry responsive to the counter for generating the override signal for terminating the memory erase sequence comprises a plurality of comparators.
Claim 4
Dependent Claim
18 words
The override timing control circuitry of claim 1 wherein the memory is a flash erasable programmable read-only memory.
Claim 5
Dependent Claim
57 words
The override timing control circuitry of claim 1 further comprising: (a) a voltage level detector for detecting when a level of the erase voltage falls below a selected voltage level; the voltage level detector terminating the memory erase sequence by disabling the override timer when the level of the erase voltage falls below the selected voltage level.
Claim 6
Independent Claim
160 words
A method for overriding a memory erase sequence controlled by a processor, comprising the steps of: (a) storing in a command register a command sent by the processor to a memory via a plurality of data pins, the command register residing on a same substrate as the memory; (b) decoding the command stored in the command register and outputting a first value if the command represents a call to initiate the memory erase sequence; (c) storing in a first latch the first value, the first latch residing on the same substrate as the memory; (d) initializing a counter and begin counting when the first value is stored in the first latch, the counter residing on the same substrate as the memory; (e) generating an override signal for terminating the memory erase sequence when the counter reaches a first count; and (f) disabling an erase voltage switch for coupling an erase voltage to the memory in response to the override signal.
Claim 7
Independent Claim
160 words
A method for overriding a memory erase sequence controlled by a processor, comprising the steps of: (a) storing in a command register a command sent by the processor to a memory via a plurality of data pins, the command register residing on a same substrate as the memory; (b) decoding the command stored in the command register and outputting a first value if the command represents a call to initiate the memory erase sequence; (c) storing in a first latch the first value, the first latch residing on the same substrate as the memory; (d) initializing a counter and begin counting when the first value is stored in the first latch, the counter residing on the same substrate as the memory; (e) generating an override signal for terminating the memory erase sequence when the counter reaches a first count; and (f) disabling an erase voltage switch for coupling an erase voltage to the memory in response to the override signal.
Claim 8
Dependent Claim
49 words
The method of claim 5 further comprising the steps of: (a) detecting when a level of the erase voltage falls below a selected voltage level; and (b) overriding the memory erase sequence by disabling the counter when the level of the erase voltage falls below the selected voltage level.
Claim 9
Dependent Claim
189 words
Override timing control circuitry for overriding a memory program sequence controlled by an external processor, the override timing control circuitry residing on a same substrate as a memory, the memory including a plurality of data pins, the override timing control circuitry comprising: (a) a command register for storing a command sent by the processor to the memory via the plurality of data pins; (b) decode circuitry coupled to the command register for decoding the command, the decode circuitry outputting a first value if the command represents a call to initiate the memory program sequence; (c) a first latch coupled to the decode circuitry for storing the first value; (d) an override timer coupled between the first latch and the memory, comprising: (1) a counter that is initialized and begins counting when the first value is stored in the first latch; (2) circuitry responsive to the counter for generating an override signal for terminating the memory program sequence when the counter reaches a first count; and (e) a program switch for controlling the application of a program voltage to the memory, the program switch being responsive to the override signal.
Claim 10
Dependent Claim
189 words
Override timing control circuitry for overriding a memory program sequence controlled by an external processor, the override timing control circuitry residing on a same substrate as a memory, the memory including a plurality of data pins, the override timing control circuitry comprising: (a) a command register for storing a command sent by the processor to the memory via the plurality of data pins; (b) decode circuitry coupled to the command register for decoding the command, the decode circuitry outputting a first value if the command represents a call to initiate the memory program sequence; (c) a first latch coupled to the decode circuitry for storing the first value; (d) an override timer coupled between the first latch and the memory, comprising: (1) a counter that is initialized and begins counting when the first value is stored in the first latch; (2) circuitry responsive to the counter for generating an override signal for terminating the memory program sequence when the counter reaches a first count; and (e) a program switch for controlling the application of a program voltage to the memory, the program switch being responsive to the override signal.
Claim 11
Dependent Claim
40 words
The override timing control circuitry of claim 7, wherein: (a) the counter comprises a plurality of flip-flops; (b) the circuitry responsive to the counter for generating the override signal for terminating the memory program sequence comprises a plurality of comparators.
Claim 12
Dependent Claim
18 words
The override timing control circuitry of claim 7 wherein the memory is a flash erasable programmable read-only memory.
Claim 13
Dependent Claim
57 words
The override timing control circuitry of claim 7 further comprising: (a) a voltage level detector for detecting when a level of the program voltage falls below a selected voltage level, the voltage level detector terminating the memory program sequence by disabling the override timer when the level of the program voltage falls below the selected voltage level.
Claim 14
Independent Claim
160 words
A method for overriding a memory program sequence controlled by a processor, comprising the steps of: (a) storing in a command register a command sent by the processor to a memory via a plurality of data pins, the command register residing on a same substrate as the memory; (b) decoding the command stored in the command register and outputting a first value when the command represents a call to initiate the memory program sequence; (c) storing in a first latch the first value, the first latch residing on the same substrate as the memory; (d) initializing a counter and begin counting when the first value is stored in the first latch, the counter residing on the same substrate as the memory; (e) generating an override signal for terminating the memory program sequence when the counter reaches a first count; and (f) disabling a program voltage switch for coupling a program voltage to the memory in response to the override signal.
Claim 15
Independent Claim
160 words
A method for overriding a memory program sequence controlled by a processor, comprising the steps of: (a) storing in a command register a command sent by the processor to a memory via a plurality of data pins, the command register residing on a same substrate as the memory; (b) decoding the command stored in the command register and outputting a first value when the command represents a call to initiate the memory program sequence; (c) storing in a first latch the first value, the first latch residing on the same substrate as the memory; (d) initializing a counter and begin counting when the first value is stored in the first latch, the counter residing on the same substrate as the memory; (e) generating an override signal for terminating the memory program sequence when the counter reaches a first count; and (f) disabling a program voltage switch for coupling a program voltage to the memory in response to the override signal.
Claim 16
Dependent Claim
49 words
The method of claim 11 further comprising the steps of: (a) detecting when a level of the program voltage falls below a selected voltage level; and (b) overriding the memory program sequence by disabling the counter when the level of the program voltage falls below the selected voltage level.
References Cited (Backward Citations)
US4439843A
Cited
US4460982A
Cited
US4718037A
Cited
US4789967A
Cited
US4791326A
Cited
US4802119A
Cited
US4958317A
Cited
US4970692A
Cited
US5050125A
Cited
US5034922A
Cited
US5053990A
Cited
US5222046A
Cited
US5043940A
Cited
US5095344A
Cited
US5155705A
Cited
US5172338A
Cited
US5297148A
Cited
US5172338B1
Cited
US5097444A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-05-08 | 1998-11-07 | 1999-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-08 | 2002-11-07 | 2003-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-08 | 2006-11-07 | 2007-05-09 | $7700.00 | Window Closed / Lapsed |