Method for selecting slew rate for a programmable device

Abstract

Abstract A system including a programmable logic device (PLD) mounted on a populated printed circuit board, and a configuration processor. The PLD includes a plurality of input/output blocks (IOBs), each having an input buffer and an output buffer. Each output buffer is coupled to an associated adjustable slew rate control circuit and to an adjustable delay line of the PLD. The configuration processor controls each of the slew rate control circuits to provide a first slew rate. The configuration processor also controls the output buffers to be coupled to the adjustable delay line. The configuration processor then controls the adjustable delay line to generate a first test pulse, which is applied to each of the output buffers. Depending on the impedances of the printed circuit board, the first test pulse transmitted from a particular output buffer may be reflected. Reflected test pulses return to the associated input buffers and are recorded. The configuration processor determines which IOBs received reflected test pulses, and which have not. The configuration processor adjusts the slew rate in the IOBs receiving a reflected test pulse, and repeats the test until there are no reflected test pulses.

Inventors

• 👤 Jesse H. Jenkins, IV

Bibliographic Details