US5740410A
Expired / Lapsed
US
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Static clock generator
Assignee: VIA Cyrix Inc
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Filing: 1995-12-15
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Granted: 1998-04-14
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Expires: 2015-12-15
Abstract
Abstract A processing system includes clock circuitry that statically multiplies/divides a stimulus signal which can then be removed while a resultant product clock is still generated, A cascaded--dual tap delay line is employed having a single phase inversion which is looped back and logically ORed with the first edge of the stimulus signal to induce oscillation. A multiplier/divisor control signal adjusts the "N" times multiplication by disabling the loop after the desired number of pulses is achieved within the period of the stimulus signal. 1/M multiplication is achieved by disabling the loop from oscillating for M stimulus clocks. Multiple frequencies can be dynamically realized on-the-fly without resynchronization by combining delayed clock pulses with a multiplexer.
Inventors
- 👤 Mark W. McDermott
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:59
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
141 words
A static clock generator comprising: (a) an edge detector having an input coupled to receive an initiating clock signal and an output; (b) a logical OR gate having first and second inputs and an output, the first input coupled to the output of the edge detector; (c) a delay line having a signal input, at least one control input, an output, and a tap between the input and the output, the output being coupled to the second input on the logical OR gate; and, (d) control logic circuitry having a plurality of inputs and at least one control output, a first input being coupled to the tap on the delay line, a second input being coupled to output of the delay line, the at least one control output being coupled to the at least one control input on the delay line.
Claim 2
Dependent Claim
141 words
A static clock generator comprising: (a) an edge detector having an input coupled to receive an initiating clock signal and an output; (b) a logical OR gate having first and second inputs and an output, the first input coupled to the output of the edge detector; (c) a delay line having a signal input, at least one control input, an output, and a tap between the input and the output, the output being coupled to the second input on the logical OR gate; and, (d) control logic circuitry having a plurality of inputs and at least one control output, a first input being coupled to the tap on the delay line, a second input being coupled to output of the delay line, the at least one control output being coupled to the at least one control input on the delay line.
Claim 3
Dependent Claim
81 words
A static clock generator comprising: (a) edge detect means for detecting a transition of an initiating clock signal; (b) logical OR means, coupled to the edge detect means, for generating an output; (c) delay line means, coupled to the logical OR means, for delaying the output and returning a regenerative feedback signal; and, (d) control logic means, coupled to the delay line means, for adjusting the delay line means to produce an output clock signal of desired frequency and duty cycle.
Claim 4
Dependent Claim
81 words
A static clock generator comprising: (a) edge detect means for detecting a transition of an initiating clock signal; (b) logical OR means, coupled to the edge detect means, for generating an output; (c) delay line means, coupled to the logical OR means, for delaying the output and returning a regenerative feedback signal; and, (d) control logic means, coupled to the delay line means, for adjusting the delay line means to produce an output clock signal of desired frequency and duty cycle.
Claim 5
Independent Claim
85 words
A method of static clock generation comprising steps of: (a) detecting a transition of an initiating clock signal and generating a pulse in response thereto; (b) logically ORing the pulse from step (a) with a regenerative feedback signal from step (c) to produce an output; (c) delaying the output from step (b) an adjustable delay time t and returning a regenerative feedback signal to step (b); and, (d) adjusting the delay time t to produce an output clock signal of desired frequency and duty cycle.
Claim 6
Independent Claim
85 words
A method of static clock generation comprising steps of: (a) detecting a transition of an initiating clock signal and generating a pulse in response thereto; (b) logically ORing the pulse from step (a) with a regenerative feedback signal from step (c) to produce an output; (c) delaying the output from step (b) an adjustable delay time t and returning a regenerative feedback signal to step (b); and, (d) adjusting the delay time t to produce an output clock signal of desired frequency and duty cycle.
Claim 7
Dependent Claim
167 words
A computer system comprising: (a) a motherboard; (b) memory disposed on the motherboard; and, (c) a processor disposed on the motherboard coupled to the memory and including a static clock generator having, (i) an edge detector having an input coupled to receive an initiating dock signal and an output; (ii) a logical OR gate having first and second inputs and an output, the first input coupled to the output of the edge detector; (iii) a delay line having a signal input, at least one control input, an output, and a tap between the input and the output, the output being coupled to the second input on the logical OR gate; and, (iv) control logic circuitry having a plurality of inputs and at least one control output, a first input being coupled to the tap on the delay line, a second input being coupled to output of the delay line, the at least one control output coupled to the at least one control input on the delay line.
Claim 8
Dependent Claim
167 words
A computer system comprising: (a) a motherboard; (b) memory disposed on the motherboard; and, (c) a processor disposed on the motherboard coupled to the memory and including a static clock generator having, (i) an edge detector having an input coupled to receive an initiating dock signal and an output; (ii) a logical OR gate having first and second inputs and an output, the first input coupled to the output of the edge detector; (iii) a delay line having a signal input, at least one control input, an output, and a tap between the input and the output, the output being coupled to the second input on the logical OR gate; and, (iv) control logic circuitry having a plurality of inputs and at least one control output, a first input being coupled to the tap on the delay line, a second input being coupled to output of the delay line, the at least one control output coupled to the at least one control input on the delay line.
Claim 9
Dependent Claim
118 words
In a computer having a motherboard, a processor, and system memory external to the processor, a method of static clock generation comprising steps of: (a) retrieving instructions from system memory; (b) executing the instructions with the processor; (c) detecting a transition of an initiating input clock signal to the processor and generating an internal pulse in response thereto; (d) logically ORing the pulse from step (c) with a regenerative feedback signal from step (e) to produce an output; (e) delaying the output from step (d) an adjustable delay time t and returning a regenerative feedback signal to step (d); and, (f) adjusting the delay time t to produce an output clock signal of desired frequency and duty cycle.
Claim 10
Dependent Claim
118 words
In a computer having a motherboard, a processor, and system memory external to the processor, a method of static clock generation comprising steps of: (a) retrieving instructions from system memory; (b) executing the instructions with the processor; (c) detecting a transition of an initiating input clock signal to the processor and generating an internal pulse in response thereto; (d) logically ORing the pulse from step (c) with a regenerative feedback signal from step (e) to produce an output; (e) delaying the output from step (d) an adjustable delay time t and returning a regenerative feedback signal to step (d); and, (f) adjusting the delay time t to produce an output clock signal of desired frequency and duty cycle.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-04-13 | 2001-10-13 | 2002-04-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-04-13 | 2005-10-13 | 2006-04-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-04-13 | 2009-10-13 | 2010-04-14 | $7700.00 | Window Closed / Lapsed |