Patent US6184072B1 successfully refreshed from Google Patents.
US6184072B1
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Process for forming a high-K gate dielectric
Assignee: NXP USA Inc
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Filing: 2000-05-17
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Granted: 2001-02-06
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Expires: 2020-05-17
Abstract
Abstract A method of processing a high K gate dielectric includes growing a high quality silicon dioxide layer at the silicon interface followed by deposition of a metal layer, which is then diffused into the silicon dioxide. Preferred metals include zirconium and hafnium. A gate stack may be fabricated by adding a metal containing layer to an existing thermally grown SiO 2 or a combination of SiO 2 , SiO 3 and SiO 4 (oxide-nitride or oxynitride) stacks.
Inventors
- 👤 Vidya S. Kaushik
- 👤 Bich-Yen Nguyen
- 👤 Olubunmi O. Adetutu
- 👤 Christopher C. Hobbs
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:12
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/691; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/0135; H10D64/681; H10D64/01336; H10D64/01344; H10D64/693
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
86 words
A method of forming a transistor on a substrate having a semiconductor surface, comprising the steps of: implanting a metal into the first portion of the surface; applying oxygen to the first portion of the surface to grow an oxide of the metal and the semiconductor surface; forming a gate conductor over the first portion of the surface; and forming a source and drain in the semiconductor surface adjacent to the gate to leave a channel between the source and drain and under the gate conductor.
Claim 2
Independent Claim
86 words
A method of forming a transistor on a substrate having a semiconductor surface, comprising the steps of: implanting a metal into the first portion of the surface; applying oxygen to the first portion of the surface to grow an oxide of the metal and the semiconductor surface; forming a gate conductor over the first portion of the surface; and forming a source and drain in the semiconductor surface adjacent to the gate to leave a channel between the source and drain and under the gate conductor.
Claim 3
Dependent Claim
21 words
The method of claim 1 , wherein the semiconductor surface is silicon and the metal is selected from hafnium and zirconium.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-02-06 | 2004-08-07 | 2005-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-02-06 | 2008-08-07 | 2009-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-02-06 | 2012-08-07 | 2013-02-06 | $7700.00 | Window Closed / Lapsed |