Patent US6182258B1 successfully refreshed from Google Patents.
US6182258B1
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Method and apparatus for test generation during circuit design
Assignee: Cadence Design Israel II Ltd
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Filing: 1998-02-06
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Granted: 2001-01-30
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Expires: 2018-02-06
Abstract
Abstract A method and apparatus are provided for functionally verifying an integrated circuit design. A hardware-oriented verification-specific object-oriented programming language is used to construct and customize verification tests. The language is extensible, and shaped to provide elements for stimulating and observing hardware device models. The invention is platform and simulator-independent, and is adapted for integration with Verilog, VHDL, and C functions. A modular system environment ensures interaction with any simulator through a unified system interface that supports multiple external types. A test generator module automatically creates verification tests from a functional description. A test suite can include any combination of statically and dynamically-generated tests. Directed generation constrains generated tests to specific functionalities. Test parameters are varied at any point during generation and random stability is supported. A checking module can perform any combination of static and dynamic checks. Incremental testing permits gradual development of test suites throughout the design development process. Customized reports of functional coverage statistics and cross coverage reports can be generated. A graphical user interface facilitates the debugging process. High-Level Verification Automation facilities, such as the ability to split and layer architecture and test files, are supported. Both verification environments and test suites can be reused.
Inventors
- 👤 Yoav Hollander
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:20
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318314; G01R31/31704; G01R31/318342; G01R31/318357; G01R31/318364; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G01R31/318307
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
76 words
An apparatus for functional verification of a device design, comprising: a test generator module for constraint based random test generation for automatically creating a verification test for said device; and a checking module for dynamic data and temporal checking a result of said test when performed on said device; wherein said design can be verified by said result; and wherein said test generator dynamically creates said test in response to a current state of said device.
Claim 2
Independent Claim
76 words
An apparatus for functional verification of a device design, comprising: a test generator module for constraint based random test generation for automatically creating a verification test for said device; and a checking module for dynamic data and temporal checking a result of said test when performed on said device; wherein said design can be verified by said result; and wherein said test generator dynamically creates said test in response to a current state of said device.
Claim 3
Dependent Claim
20 words
The apparatus of claim 1 , wherein said device is a simulation of any of a module, chip, and system.
Claim 4
Dependent Claim
20 words
The apparatus of claim 2 , further comprising a formal verification extension module for verifying said simulation of said device.
Claim 5
Dependent Claim
31 words
The apparatus of claim 1 , further comprising: an interactive debugging module for displaying data events and the interrelations of said data events, and for permitting modifications to said device design.
Claim 6
Dependent Claim
20 words
The apparatus of claim 1 , further comprising a reporting module for generating reports regarding said test and said device.
Claim 7
Dependent Claim
20 words
The apparatus of claim 1 , wherein said apparatus is operable to perform either of cycle-based or event driven testing.
Claim 8
Dependent Claim
18 words
The apparatus of claim 1 , wherein said test generator automatically creates a test from a functional description.
Claim 9
Dependent Claim
21 words
The apparatus of claim 1 , further comprising a verification specific object-oriented programming language for constructing and customizing said verification tests.
Claim 10
Dependent Claim
23 words
The apparatus of claim 1 , further comprising means to constrain the functional scope of said verification test generated by said test generator.
Claim 11
Dependent Claim
25 words
The apparatus of claim 1 , wherein said apparatus is operable to perform any combination of deterministic tests, random tests, dynamic tests, and static tests.
Claim 12
Dependent Claim
12 words
The apparatus of claim 1 , wherein said apparatus supports random stability.
Claim 13
Dependent Claim
25 words
The apparatus of claim 1 , further comprising an co-verification extension module for performing co-verification of said device under testing and an external software program.
Claim 14
Dependent Claim
13 words
The apparatus of claim 1 , wherein said test generator pre-simulates said test.
Claim 15
Independent Claim
101 words
An apparatus for functional verification of a device design, comprising: a test generator module for constraint based random test generation for automatically creating a verification test for said device; a checking module for dynamic data and temporal checking a result of said test when performed on said device; a debugging module for displaying data events and the interrelations of said data events; and a reporting module for generating reports regarding said test and said device; wherein said apparatus uses a verification specific object-oriented programming language to construct and customize said verification tests; wherein said design can be verified by said result.
Claim 16
Independent Claim
101 words
An apparatus for functional verification of a device design, comprising: a test generator module for constraint based random test generation for automatically creating a verification test for said device; a checking module for dynamic data and temporal checking a result of said test when performed on said device; a debugging module for displaying data events and the interrelations of said data events; and a reporting module for generating reports regarding said test and said device; wherein said apparatus uses a verification specific object-oriented programming language to construct and customize said verification tests; wherein said design can be verified by said result.
Claim 17
Dependent Claim
20 words
The apparatus of claim 14 , wherein said device is a simulation of any of a module, chip, and system.
Claim 18
Dependent Claim
20 words
The apparatus of claim 15 , further comprising a formal verification extension module for verifying said simulation of said device.
Claim 19
Dependent Claim
13 words
The apparatus of claim 14 , wherein said test generator pre-simulates said test.
Claim 20
Dependent Claim
23 words
The apparatus of claim 14 , wherein said test generator dynamically creates said test in response to a current state of said device.
Claim 21
Dependent Claim
20 words
The apparatus of claim 14 , wherein said apparatus is operable to perform either of cycle-based or event driven testing.
Claim 22
Dependent Claim
18 words
The apparatus of claim 14 , wherein said test generator automatically creates a test from a functional description.
Claim 23
Dependent Claim
23 words
The apparatus of claim 14 , further comprising means to constrain the functional scope of said verification test generated by said test generator.
Claim 24
Dependent Claim
25 words
The apparatus of claim 14 , wherein said apparatus is operable to perform any combination of deterministic tests, random tests, dynamic tests, and static tests.
Claim 25
Dependent Claim
12 words
The apparatus of claim 14 , wherein said apparatus supports random stability.
Claim 26
Dependent Claim
25 words
The apparatus of claim 14 , further comprising an co-verification extension module for performing co-verification of said device under testing and an external software program.
Claim 27
Independent Claim
101 words
A method for functionally verifying a device design, comprising the steps of: automatically creating a verification test for said device with a test generator module for constraint based random test generation; using a verification specific object-oriented programming language to construct and customize said verification tests; dynamic data and temporal checking with a checking module a result of said test when performed on said device; displaying data events and the interrelations of said data events using an interactive debugging module; and generating with a reporting module reports regarding said device and said tests; wherein said design can be verified by said result.
Claim 28
Independent Claim
101 words
A method for functionally verifying a device design, comprising the steps of: automatically creating a verification test for said device with a test generator module for constraint based random test generation; using a verification specific object-oriented programming language to construct and customize said verification tests; dynamic data and temporal checking with a checking module a result of said test when performed on said device; displaying data events and the interrelations of said data events using an interactive debugging module; and generating with a reporting module reports regarding said device and said tests; wherein said design can be verified by said result.
Claim 29
Dependent Claim
21 words
The method of claim 25 , wherein said device is a simulation of any of a simulation, module, chip, and system.
Claim 30
Dependent Claim
23 words
The method of claim 26 , further comprising the step of verifying said simulation of said device using a formal verification extension module.
Claim 31
Dependent Claim
22 words
The method of claim 25 , wherein, in said step of automatically creating a verification test, said test generator pre-simulates said test.
Claim 32
Dependent Claim
32 words
The method of claim 25 , wherein, in said step of automatically creating a verification test, said test generator dynamically creates said test in response to a current state of said device.
Claim 33
Dependent Claim
22 words
The method of claim 25 , further comprising the step of said test generator generating either of cycle-based or event driven testing.
Claim 34
Dependent Claim
27 words
The method of claim 25 , wherein, in said step of automatically creating a verification test, said test generator automatically creates a test from a functional description.
Claim 35
Dependent Claim
23 words
The method of claim 25 , further comprising thr step of constraining the functional scope of said verification test generated by said generator.
Claim 36
Dependent Claim
26 words
The method of claim 25 , comprising the step of performing on said device any combination of deterministic tests, random tests, dynamic tests, and static tests.
Claim 37
Dependent Claim
17 words
The method of claim 25 , further comprising the step of supporting random stability in said test.
Claim 38
Dependent Claim
28 words
The method of claim 25 , further comprising the step of performing co-verification of said device under testing and an external software program using a co-verification extension module.
References Cited (Backward Citations)
US4862399A
Cited
US5159600A
Cited
US5933356A
Cited
US5202889A
Cited
US5446742A
Cited
US5751592A
Cited
US5394347A
Cited
US5488573A
Cited
US5530804A
Cited
US5600579A
Cited
US5568407A
Cited
US5630051A
Cited
US5784593A
Cited
US5740353A
Cited
US5859962A
Cited
US5774358A
Cited
US5646949A
Cited
US5903475A
Cited
US5729554A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-30 | 2004-07-31 | 2005-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-30 | 2008-07-31 | 2009-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-30 | 2012-07-31 | 2013-01-30 | $7700.00 | Window Closed / Lapsed |