Digital matched filter

Claim 2

A digital matched filter for determining a correlation value between an N-bit digital signal, which is synchronous with a clock, and a digital code sequence which includes M digital codes, comprising: a) first to M-th digital signal storing means applied with said N-bit digital signal; b) digital write selection means for sequentially selecting said first to M-th digital signal storing means one by one in synchronism with said clock to store said N-bit digital signal in the selected digital signal storing means; c) a recursive shift register for digital code sequence having first to M-th stages of code flip-flops connected in cascade, and being operative in synchronism with said clock, wherein said M digital codes are stored in said first to M-th stages of code flip-flops, respectively, and an output terminal of said M-th stage of code flip-flop is connected to an input terminal of said first stage of code flip-flop; d) first to M-th digital multiplication means for multiplying output signals of said first to M-th digital signal storing means by output signals of said first to M-th stages of code flip-flops, respectively; and e) digital addition means for adding output signals of said first to M-th digital multiplication means.

Claim 3

A digital matched filter according to claim 1 , wherein each of said first to M-th digital signal storing means includes N flip-flops which are connected in parallel and are operative in synchronism with said clock; said digital write selection means includes: a write selecting recursive shift register having first to M-th stages of write selecting flip-flops connected in cascade, and being operative in synchronism with said clock, wherein an output signal of said M-th stage of write selecting flip-flop being applied to said first stage of write selecting flip-flop; and upon start of operation, a signal for selecting said digital signal storing means is stored in desired one of said first to M-th stages of write selecting flip-flops.

Claim 4

A digital matched filter according to claim 1 , wherein each of said first to M-th digital signal storing means includes N flip-flops which are connected in parallel and are operative in synchronism with said clock; and said digital write selecting means includes: first to M-th stages of write selecting flip-flops connected in cascade, reset before start of operation, and operated in synchronism with said clock after start of operation; and a digital selection circuit outputting a signal for selecting said digital signal storing means to said first stage of write selecting flip-flop during only a period shorter than one period of said clock after start of operation, and outputting an output signal of said M-th stage of write selecting flip-flop to said first stage of write selecting flip-flop after said period has elapsed.

Claim 5

A digital matched filter according to claim 1 , wherein said first to M-th digital signal storing means include first to M-th memories of N bits, and said digital write selecting means includes an address counter which counts said clock to sequentially output addresses of said first to M-th memories in synchronism with said clock.

Claim 6

A digital matched filter for determining a correlation value between an N-bit digital signal, which is over-sampled by a first clock having a frequency which is m-times as large as a second clock, and a digital code sequence which includes M digital codes, comprising: a) m×M digital signal storing means applied with said N-bit digital signal; b) digital write selecting means for sequentially selecting said m×M digital signal storing means one by one in synchronism with said first clock to store said N-bit digital signal in the selected digital signal storing means; c) first to M-th digital selection means dividing said m×M digital signal storing means by m to divide said m×M digital signal storing means into M blocks to sequentially select and output output signals of said m digital signal storing means included in said M blocks within one period of said second clock; d) a recursive shift register for digital code sequence having first to M-th stages of code flip-flops which are connected in cascade, and being operative in synchronism with said second clock, wherein said M digital codes are stored in said first to M-th staged of code flip-flops, respectively, and an output terminal of said M-th stage of code flip-flop is connected to an input terminal of said first stage of code flip-flop; e) first to M-th digital multiplication means for multiplying output signals of said first to M-th digital selection means by output signals of said first to M-th stages of code flip-flops, respectively; and f) digit al addition means for adding output signals of said first to M-th digital multiplication means.

Claim 7

A digital matched filter for determining a correlation value between an N-bit digital signal, which is over-sampled by a first clock having a frequency which is m-times as large as a second clock, and a digital code sequence which includes M digital codes, comprising: a) m×M digital signal storing means applied with said N-bit digital signal; b) digital write selecting means for sequentially selecting said m×M digital signal storing means one by one in synchronism with said first clock to store said N-bit digital signal in the selected digital signal storing means; c) first to M-th digital selection means dividing said m×M digital signal storing means by m to divide said m×M digital signal storing means into M blocks to sequentially select and output output signals of said m digital signal storing means included in said M blocks within one period of said second clock; d) a recursive shift register for digital code sequence having first to M-th stages of code flip-flops which are connected in cascade, and being operative in synchronism with said second clock, wherein said M digital codes are stored in said first to M-th staged of code flip-flops, respectively, and an output terminal of said M-th stage of code flip-flop is connected to an input terminal of said first stage of code flip-flop; e) first to M-th digital multiplication means for multiplying output signals of said first to M-th digital selection means by output signals of said first to M-th stages of code flip-flops, respectively; and f) digit al addition means for adding output signals of said first to M-th digital multiplication means.

Claim 8

A digital matched filter according to claim 5 , wherein each of said m×M digital signal storing means includes N flip-flops which are connected in parallel and are operative in synchronism with said first clock, and said digital write selection means includes: a write selecting recursive shift register having first to (m×M)-th stages of write selecting flip-flops connected in cascade, and being operative in synchronism with said first clock, wherein an output signal of said (m×M)-th stage of write selecting flip-flop being applied to said first stage of write selecting flip-flop; and upon start of operation, a signal for selecting said digital signal storing means is stored in desired one of said first to (m×M)-th stages of write selecting flip-flops.

Claim 9

A digital matched filter according to claim 5 , wherein each of said m×M digital signal storing means includes N flip-flops which are connected in parallel and are operative in synchronism with said first clock, and said digital write selection means includes: first to (m×M)-th stages of write selecting flip-flops connected in cascade, reset before start of operation, and operated in synchronism with said first clock after start of operation; and a digital selection circuit outputting a signal for selecting said digital signal storing means to said first stage of write selecting flip-flop during only a period shorter than one period of said first clock after start of operation, and outputting an output signal of said (m×M)-th stage of write selecting flip-flop to said first stage of write selecting flip-flop after said period has elapsed.

Claim 10

A digital matched filter according to claim 5 , wherein said m×M digital signal storing means include m×M memories of N bits, and said digital write selection means includes an address counter which counts said first clock to sequentially output addresses of said m×M memories in synchronism with said first clock.

Claim 11

A digital matched filter for determining a correlation value between an N-bit digital signal, which is over-sampled by a first clock having a frequency which is m-times as large as a second clock, and a digital code sequence which includes M digital codes, comprising: a) serial/parallel conversion means for serial/parallel converting said digital signal serially inputted to output first to m-th digital signals in parallel; b) first to m-th digital signal storage means applied with said first to m-th digital signals from said serial/parallel conversion means, respectively, and having each M memory units; c) digital write selection means for sequentially selecting said M memory units one by one in synchronism with said second clock every said first to m-th digital storage means to store said respective first to M-th digital signals in said respective selected memory units; d) first to M-th digital selection means for sequentially selecting and outputting output signals of said first to m-th digital signal storing means within one period of said second clock every said M memory units, respectively; e) a recursive shift register for digital code sequence having first to M-th stages of code flip-flops which are connected in cascade, and being operative in synchronism with said second clock, wherein said M digital codes are stored in said first to M-th stages of code flip-flops, respectively, and an output terminal of said M-th stage of code flip-flop is connected to an input terminal of said first stage of code flip-flop; f) first to M-th digital multiplication means for multiplying output signals of said first to M-th digital selection means by output signals of said first to M-th stages of code flip-flops, respectively; and g) digital addition means for adding output signals of said first to M-th digital multiplication means.

Claim 12

A digital matched filter for determining a correlation value between an N-bit digital signal, which is over-sampled by a first clock having a frequency which is m-times as large as a second clock, and a digital code sequence which includes M digital codes, comprising: a) serial/parallel conversion means for serial/parallel converting said digital signal serially inputted to output first to m-th digital signals in parallel; b) first to m-th digital signal storage means applied with said first to m-th digital signals from said serial/parallel conversion means, respectively, and having each M memory units; c) digital write selection means for sequentially selecting said M memory units one by one in synchronism with said second clock every said first to m-th digital storage means to store said respective first to M-th digital signals in said respective selected memory units; d) first to M-th digital selection means for sequentially selecting and outputting output signals of said first to m-th digital signal storing means within one period of said second clock every said M memory units, respectively; e) a recursive shift register for digital code sequence having first to M-th stages of code flip-flops which are connected in cascade, and being operative in synchronism with said second clock, wherein said M digital codes are stored in said first to M-th stages of code flip-flops, respectively, and an output terminal of said M-th stage of code flip-flop is connected to an input terminal of said first stage of code flip-flop; f) first to M-th digital multiplication means for multiplying output signals of said first to M-th digital selection means by output signals of said first to M-th stages of code flip-flops, respectively; and g) digital addition means for adding output signals of said first to M-th digital multiplication means.

Claim 13

A digital matched filter according to claim 9 , wherein each of said M memory units of said first to m-th digital signal storing means includes N flip-flops which are connected in parallel and being operative in synchronism with said second clock; said digital write selection means includes: first to m-th write selecting recursive shift registers each having first to M-th write selecting flip-flops connected in cascade, and being operative in synchronism with said second clock, wherein an output signal of said M-stage of write selecting flip-flop being applied to said first stage of write selecting flip-flop; and upon start of operation, signals for selecting said M memory units of said first to m-th digital signal storing means are stored in desired ones of said first to M-th stages of write selecting flip-flops of said first to m-th write selecting recursive shift registers, respectively.

Claim 14

A digital matched filter according to claim 9 , wherein each of said M memory units of said first to m-th digital signal storing means includes N flip-flops which are connected in parallel and are operative in synchronism with said second clock, and said digital write selection means includes: first to m-th write selecting shift registers each having first to M-th stages of write selecting flip-flops connected in cascade, reset before start of operation, and operated in synchronism with said second clock after start of operation; and first to m-th digital selection circuits for outputting signals for selecting said M memory units of said first to m-th digital signal storing means to said first to M-th stages of write selecting flip-flops of said first to m-th write selecting shift registers, respectively, during only a shorter period than one period of said second clock after start of operation, and for outputting output signals of said M-th stages of write selecting flip-flops of said first to m-th write selecting shift registers to said first stages of write selecting flip-flops of said respective first to m-th write selecting shift registers after said period has elapsed.

Claim 15

A digital matched filter according to claim 9 , wherein each of said M memory units of said respective first to m-th digital signal storing means includes a digital signal storing memory of N bits, and said digital write selection means includes an address counter for counting said second clock to sequentially output addresses of said digital signal storing memories in synchronism with said second clock every said first to m-th digital signal storing means.