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US4025772A Expired / Lapsed US ⏱️ 0.0 years remaining

Digital convolver matched filter and correlator

Assignee: CONSTANT ARGEREY 1603 DANBURY DRIVE CLAREMONT CA 91711
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Filing: 1975-07-11
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Granted: 1977-05-24
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Expires: 1995-07-11
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Abstract

Abstract A system for digital signal processing, including a random access memory (RAM) accessed by counters and used for storing and shifting signals in a convolver, correlator, matched filter or multiplier. An input signal and a reference signal are applied from opposite ends of the device such that the signals scan past each other at a relative velocity with respect to each other for obtaining either the convolution or correlation function of signals. The RAM operates as a shift register delay line and provides time scale inversion of signals when desired.

Inventors

  • 👤 James Nickolas Constant

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 19:27
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/15

Claims Analysis

Total Claims: 24
Claim 1
Independent Claim 236 words
In a system for the digital implementation of convolvers, matched filters, correlators and multipliers, the combination of: a first digital delay means having a first random access memory for storing first signals in a first time sequence, said first memory having storage locations for N words; a second digital delay means having a second memory for storing second signals, said second memory having storage locations for N words; an address counter connected to said memories for addressing N corresponding storage locations of said first and second memories in a sampling interval providing N pairs of outputs in sequence, with each output of a pair of outputs being one of the time sequence or time-reverse sequence of said first time sequence; clock means connected to said memories and to said address counter for controlling timing operations of said first and second memories and of said address counter, including means for shifting at least said first signals in said first memory after each sampling interval; multiplier means having as its input the N pairs of outputs of said first and said second memories and providing at its output the serial word-by-word product of said first and said second signals; and integrator means having said multiplier means output as an input for integrating the product over a number of sampling intervals and providing at its output one of the convolution or correlation of said first and said second signals.
Claim 2
Dependent Claim 236 words
In a system for the digital implementation of convolvers, matched filters, correlators and multipliers, the combination of: a first digital delay means having a first random access memory for storing first signals in a first time sequence, said first memory having storage locations for N words; a second digital delay means having a second memory for storing second signals, said second memory having storage locations for N words; an address counter connected to said memories for addressing N corresponding storage locations of said first and second memories in a sampling interval providing N pairs of outputs in sequence, with each output of a pair of outputs being one of the time sequence or time-reverse sequence of said first time sequence; clock means connected to said memories and to said address counter for controlling timing operations of said first and second memories and of said address counter, including means for shifting at least said first signals in said first memory after each sampling interval; multiplier means having as its input the N pairs of outputs of said first and said second memories and providing at its output the serial word-by-word product of said first and said second signals; and integrator means having said multiplier means output as an input for integrating the product over a number of sampling intervals and providing at its output one of the convolution or correlation of said first and said second signals.
Claim 3
Dependent Claim 44 words
The system of claim 1 wherein said multiplier means is a set of m EXCL OR multipliers for the serial word-by-word multiplication of said first and second signals, and wherein said integrator means is a low pass filter for integrating products of said signals.
Claim 4
Dependent Claim 40 words
The system of claim 1 wherein said integrator means includes means having as its input the input and output of said integrator means and providing at its output the product of said first and second signals at t = 0.
Claim 5
Dependent Claim 27 words
The system of claim 1 wherein said multiplier means includes a set of m multipliers for the serial word-by-word multiplication of said first and said second signals.
Claim 6
Dependent Claim 24 words
The system of claim 1 wherein said clock means includes means for shifting said second signals in said second memory after each sampling interval.
Claim 7
Dependent Claim 19 words
The system of claim 1 wherein said first and second memories include one of a TTL, CCD, and ECL.
Claim 8
Dependent Claim 14 words
The system of claim 1 wherein said first digital delay means is a RAM.
Claim 9
Dependent Claim 15 words
The system of claim 1 wherein said first digital delay means is a DELTIC RAM.
Claim 10
Dependent Claim 27 words
The system of claim 1 wherein said second digital delay means is a RAM, and wherein said address counter is connected to said RAM for addressing same.
Claim 11
Dependent Claim 29 words
The system of claim 1 wherein said second digital delay means is a DELTIC RAM, and wherein said address counter is connected to said DELTIC RAM for addressing same.
Claim 12
Dependent Claim 27 words
The system of claim 1 wherein said second digital delay means is a ROM, and wherein said address counter is connected to said ROM for addressing same.
Claim 13
Dependent Claim 29 words
The system of claim 1 wherein said second digital delay means is a DELTIC ROM, and wherein said address counter is connected to said DELTIC ROM for addressing same.
Claim 14
Dependent Claim 27 words
The system of claim 1 wherein said second digital delay means is a PROM, and wherein said address counter is connected to said PROM for addressing same.
Claim 15
Dependent Claim 29 words
The system of claim 1 wherein said second digital delay means is a DELTIC PROM, and wherein said address counter is connected to said DELTIC PROM for addressing same.
Claim 16
Dependent Claim 14 words
The system of claim 1 wherein said second digital delay means is a BSR.
Claim 17
Dependent Claim 15 words
The system of claim 1 wherein said second digital delay means is a DELTIC BSR.
Claim 18
Dependent Claim 19 words
The system of claim 1 wherein said second digital delay means comprises means providing a set of bipolar voltages.
Claim 19
Independent Claim 157 words
A method for the digital implementation of convolvers, matched filters, correlators and multipliers, including the steps of: storing first signals in a first time sequence in a first random access memory having storage locations for N words; storing second signals in a second memory having storage locations for N words; addressing corresponding storage locations of the first memory and the second memory in a sampling interval and providing N pairs of outputs in sequence, with each output of a pair of outputs being one of the time sequence or time-reverse sequence of said first time sequence; serially multiplying the N pairs of outputs from said first and second memories to produce the word-by-word product of said signals; shifting at least the first signals in the first memory after each sampling interval; and integrating the products of multiplication over a number of sampling intervals to produce one of the convolution or correlation of the first and second signals.
Claim 20
Independent Claim 157 words
A method for the digital implementation of convolvers, matched filters, correlators and multipliers, including the steps of: storing first signals in a first time sequence in a first random access memory having storage locations for N words; storing second signals in a second memory having storage locations for N words; addressing corresponding storage locations of the first memory and the second memory in a sampling interval and providing N pairs of outputs in sequence, with each output of a pair of outputs being one of the time sequence or time-reverse sequence of said first time sequence; serially multiplying the N pairs of outputs from said first and second memories to produce the word-by-word product of said signals; shifting at least the first signals in the first memory after each sampling interval; and integrating the products of multiplication over a number of sampling intervals to produce one of the convolution or correlation of the first and second signals.
Claim 21
Dependent Claim 21 words
The method of claim 18 including the step of shifting the second signals in the second memory after each sampling interval.
Claim 22
Dependent Claim 19 words
The method of claim 18 including the step of multiplying said first and second signals at t = 0.
Claim 23
Dependent Claim 21 words
The method of claim 18 wherein the first signals are stored in a first random access memory comprising a DELTIC circuit.
Claim 24
Dependent Claim 19 words
The method of claim 18 wherein the second signals are stored in a second memory comprising a DELTIC circuit.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1980-05-23 1980-11-22 1981-05-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1984-05-23 1984-11-22 1985-05-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1988-05-23 1988-11-22 1989-05-24 $7700.00 Window Closed / Lapsed

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