Patent US6470496B1 successfully refreshed from Google Patents.
Patent US6175946B1 successfully refreshed from Google Patents.
US6175946B1
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Method for automatically generating checkers for finding functional defects in a description of a circuit
Assignee: Mentor Graphics Corp
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Filing: 1997-10-20
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Granted: 2001-01-16
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Expires: 2017-10-20
Abstract
Abstract A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers. Some of the checkers may use signals generated by other checkers.
Inventors
- 👤 Tai An Ly
- 👤 Jean-Charles Giomi
- 👤 Kalyana C. Mulam
- 👤 Paul Andrew Wilcox
- 👤 David Lansing Dill
- 👤 II Paul Estrada
- 👤 Chian-Min Richard Ho
- 👤 Jing Chyuarn Lin
- 👤 Robert Kristianto Mardjuki
- 👤 Lawrence Curtis Widdoes, Jr.
- 👤 Ping Fai Yeung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:21
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
73 words
A method for functional verification, said method being implemented in a programmed computer, said method comprising: automatically generating instructions that represent a checker for flagging a predetermined defective behavior of a device represented in a description of a circuit to be functionally verified; and simulating the behavior of said device and of said checker, wherein during simulation said checker monitors signals to or from the device for conformance with the predetermined defective behavior.
Claim 2
Independent Claim
73 words
A method for functional verification, said method being implemented in a programmed computer, said method comprising: automatically generating instructions that represent a checker for flagging a predetermined defective behavior of a device represented in a description of a circuit to be functionally verified; and simulating the behavior of said device and of said checker, wherein during simulation said checker monitors signals to or from the device for conformance with the predetermined defective behavior.
Claim 3
Dependent Claim
82 words
The method of claim 1 further comprising: converting said description into a graph including at least a first node representing a first storage element, and a second node representing a second storage element; and said predetermined defective behavior requires that if a first data in said first storage element is different from a second data in said second storage element, said first data is loaded into said second storage element prior to loading of said second data into a third storage element.
Claim 4
Dependent Claim
31 words
The method of claim 2 further comprising: automatically determining a condition imposed by said description for retaining said second data in said second storage element, said condition is not always false.
Claim 5
Dependent Claim
32 words
The method of claim 2 wherein: during said converting, each call to a module in a hierarchy of modules is automatically instantiated as often as necessary until the graph is completely flattened.
Claim 6
Dependent Claim
60 words
The method of claim 1 , wherein said description includes a plurality of variables, the method further comprising: automatically determining that at least one variable represents a storage element, said storage element containing a current data; and automatically determining a condition imposed by said description for retaining said current data in said storage element, said condition is not always false.
Claim 7
Dependent Claim
45 words
The method of claim 1 , wherein said predetermined defective behavior is a first behavior, said method further comprising: automatically generating second instructions for flagging a second predetermined defective behavior of other circuit elements, said second instructions using a signal generated by said first instructions.
Claim 8
Dependent Claim
18 words
The method of claim 1 wherein: said device includes a counter; and said checker is a counter checker.
Claim 9
Dependent Claim
19 words
The method of claim 1 wherein: said device includes a three-state circuit; and said checker is a three-state checker.
Claim 10
Dependent Claim
19 words
The method of claim 1 wherein: said device includes a memory location; and said checker is a memory checker.
Claim 11
Dependent Claim
19 words
The method of claim 1 wherein: said device includes a case arrangement; and said checker is a case checker.
Claim 12
Independent Claim
225 words
A method for generating a checker for finding functional defects in a description of a first circuit, said method being implemented in a programmed computer, said method comprising: converting said description into a graph, said graph including a plurality of nodes, and a plurality of connections among said nodes; examining said graph for an instance of a predetermined arrangement of said nodes and connections; generating instructions for flagging a functional behavior of a device represented by said instance in conformance with a predetermined defective behavior; wherein said graph includes a first node for a storage element and a second node for a statement in said description, said statement describing a condition for branching to one or more of a plurality of items, or for branching to none of said items, said first node being connected by a first connection to said second node, said first node being further connected to a second connection for carrying a control signal, said control signal being indicative of a load condition for loading a data signal from said first connection into said first node; and said step of generating instructions generates instructions for flagging the behavior of an instance of said first node and said second node when said load condition is the logic value TRUE and said condition of said statement describes branching to none of said items.
Claim 13
Independent Claim
225 words
A method for generating a checker for finding functional defects in a description of a first circuit, said method being implemented in a programmed computer, said method comprising: converting said description into a graph, said graph including a plurality of nodes, and a plurality of connections among said nodes; examining said graph for an instance of a predetermined arrangement of said nodes and connections; generating instructions for flagging a functional behavior of a device represented by said instance in conformance with a predetermined defective behavior; wherein said graph includes a first node for a storage element and a second node for a statement in said description, said statement describing a condition for branching to one or more of a plurality of items, or for branching to none of said items, said first node being connected by a first connection to said second node, said first node being further connected to a second connection for carrying a control signal, said control signal being indicative of a load condition for loading a data signal from said first connection into said first node; and said step of generating instructions generates instructions for flagging the behavior of an instance of said first node and said second node when said load condition is the logic value TRUE and said condition of said statement describes branching to none of said items.
Claim 14
Dependent Claim
33 words
The method of claim 11 further comprising: during said converting, each call to a module in a hierarchy of modules is automatically instantiated as often as necessary until the graph is completely flattened.
Claim 15
Independent Claim
139 words
A method for generating a checker for finding functional defects in a description of a circuit, said method being implemented in a programmed computer, said method comprising: converting the description into a graph, the graph including a plurality of nodes, and a plurality of connections among the nodes, the graph including a first node for a storage element and a second node for a statement in the description, the first node being connected by a first connection to the second node, the first node being further connected to a second connection for carrying a control signal, the control signal being indicative of a load condition for loading a data signal from the first connection into the first node; generating instructions for flagging a functional behavior of a device represented in the description in conformance with a predetermined defective behavior.
Claim 16
Independent Claim
139 words
A method for generating a checker for finding functional defects in a description of a circuit, said method being implemented in a programmed computer, said method comprising: converting the description into a graph, the graph including a plurality of nodes, and a plurality of connections among the nodes, the graph including a first node for a storage element and a second node for a statement in the description, the first node being connected by a first connection to the second node, the first node being further connected to a second connection for carrying a control signal, the control signal being indicative of a load condition for loading a data signal from the first connection into the first node; generating instructions for flagging a functional behavior of a device represented in the description in conformance with a predetermined defective behavior.
Claim 17
Dependent Claim
14 words
The method of claim 13 wherein: the statement describes at least an arithmetic expression.
Claim 18
Dependent Claim
11 words
The method of claim 14 wherein: the arithmetic expression includes incrementing.
Claim 19
Dependent Claim
14 words
The method of claim 13 wherein: the statement describes at least another storage element.
Claim 20
Dependent Claim
19 words
The method of claim 13 wherein: the statement describes a condition for setting a signal on the first connection.
Claim 21
Dependent Claim
13 words
The method of claim 13 wherein: the statement describes a condition for branching.
Claim 22
Independent Claim
227 words
A method for generating a checker for finding functional defects in a description of a first circuit, said method being implemented in a programmed computer, said method comprising: converting said description into a graph, said graph including a plurality of nodes, and a plurality of connections among said nodes; examining said graph for an instance of a predetermined arrangement of said nodes and connections; generating instructions for flagging a functional behavior of a device represented by said instance in conformance with a predetermined defective behavior; wherein said graph includes a first node for a storage element and a second node for a statement in said description, said statement describing a condition for branching to one or more of a plurality of items, or for branching to none of said items, said first node being connected by a first connection to said second node, said first node being further connected to a second connection for carrying a control signal, said control signal being indicative of a load condition for loading a data signal from said first connection into said first node; and said step of generating instructions generates instructions for flagging the behavior of an instance of said first node and said second node when said load condition is the logic value TRUE and said condition of said statement describes branching to more than one of said items.
Claim 23
Independent Claim
227 words
A method for generating a checker for finding functional defects in a description of a first circuit, said method being implemented in a programmed computer, said method comprising: converting said description into a graph, said graph including a plurality of nodes, and a plurality of connections among said nodes; examining said graph for an instance of a predetermined arrangement of said nodes and connections; generating instructions for flagging a functional behavior of a device represented by said instance in conformance with a predetermined defective behavior; wherein said graph includes a first node for a storage element and a second node for a statement in said description, said statement describing a condition for branching to one or more of a plurality of items, or for branching to none of said items, said first node being connected by a first connection to said second node, said first node being further connected to a second connection for carrying a control signal, said control signal being indicative of a load condition for loading a data signal from said first connection into said first node; and said step of generating instructions generates instructions for flagging the behavior of an instance of said first node and said second node when said load condition is the logic value TRUE and said condition of said statement describes branching to more than one of said items.
Claim 24
Dependent Claim
33 words
The method of claim 19 further comprising: during said converting, each call to a module in a hierarchy of modules is automatically instantiated as often as necessary until the graph is completely flattened.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-16 | 2004-07-17 | 2005-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-16 | 2008-07-17 | 2009-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-16 | 2012-07-17 | 2013-01-16 | $7700.00 | Window Closed / Lapsed |