US5654657A
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Accurate alignment of clocks in mixed-signal tester
Assignee: Credence Systems Corp
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Filing: 1995-08-01
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Granted: 1997-08-05
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Expires: 2015-08-01
Abstract
Abstract Asynchronously-generated digital and analog clocks in a mixed-signal test system are accurately aligned for repeatable and deterministic testing. A variable-frequency digital master clock signal is used in direct digital synthesis of an analog clock signal which is asynchronous to the master clock signal. A resync command inhibits the analog clock signal until the analog clock signal is in a desired phase relationship to the master clock signal. The analog clock signal is thus phase-aligned with the master clock signal in a known and deterministic relationship. The resync command also aligns the phase of the analog clock signal with the pattern of stimulus signals applied to the device under test. Aligning the analog clock signal with the master clock signal and with the stimulus pattern assures that test results are consistent from test-to-test. A phase-locked loop removes spurs from the synthesized analog clock signal. A jitter generator is provided for controlled jittering of the analog clock signal as needed for some types of test. An Nth occurrence counter allows for programmable introduction of an extra master-clock signal period in the test pattern when needed to avoid creating a metastable condition in the device under test.
Inventors
- 👤 Stuart Robert Pearce
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:22
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31708; G01R31/31709; G01R31/3167; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31922; H; H03; H03K; H03K5/00; H03K5/13; H03K5/135; H03L; H03L7/00
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
74 words
A method of aligning the relative phase of asynchronous clock signals, comprising the steps of: a. generating a master clock signal, b. generating by direct digital synthesis a second clock signal asynchronous with the master clock signal when enabled by a resynchronization signal; and c. producing said resynchronization signal which enables generation of the second clock signal such that the second clock signal is in a determined phase relationship to the master clock signal.
Claim 2
Independent Claim
74 words
A method of aligning the relative phase of asynchronous clock signals, comprising the steps of: a. generating a master clock signal, b. generating by direct digital synthesis a second clock signal asynchronous with the master clock signal when enabled by a resynchronization signal; and c. producing said resynchronization signal which enables generation of the second clock signal such that the second clock signal is in a determined phase relationship to the master clock signal.
Claim 3
Dependent Claim
56 words
The method of claim 1, further comprising aligning the relative phase of the second clock signal to a test vector pattern in a mixed-signal tester by producing the resynchronization signal so as to enable generation of the second clock signal when the second clock signal is in a determined phase relationship to the test vector pattern.
Claim 4
Dependent Claim
20 words
The method of claim 1, wherein generating a master clock signal comprises generating a digital clock signal of variable frequency.
Claim 5
Dependent Claim
43 words
The method of claim 3, wherein generating a second clock signal comprises deriving the second clock signal by direct digital synthesis from the master clock signal so that frequency of the second clock signal varies with frequency variation in the master clock signal.
Claim 6
Dependent Claim
50 words
The method of claim 1, further comprising the step of gating the second clock signal to a clock-generator output such that the second clock signal is allowed to stabilize for an interval after being enabled by the resynchronization signal and is then passed to the clock-generator output after said interval.
Claim 7
Dependent Claim
44 words
The method of claim 2, wherein phase of the test vector pattern is indicated by a trigger, and further comprising the steps of counting a number N of clock events following the trigger and then inserting a programmed delay in the test vector pattern.
Claim 8
Dependent Claim
32 words
The method of claim 1, wherein the steps of generating the master clock signal, generating the second clock signal, and producing the resynchronization signal, are carried out in a mixed-signal integrated-circuit tester.
Claim 9
Dependent Claim
72 words
Apparatus for aligning the relative phase of asynchronous clock signals, comprising: a. a master clock signal source; b. a digital synthesizer for generating a second clock signal asynchronous with the master clock signal when enabled by a resynchronization signal; and c. a source of said resynchronization signal which enables generation of the second clock signal such that the second clock signal is in a determined phase relationship to the master clock signal.
Claim 10
Dependent Claim
72 words
Apparatus for aligning the relative phase of asynchronous clock signals, comprising: a. a master clock signal source; b. a digital synthesizer for generating a second clock signal asynchronous with the master clock signal when enabled by a resynchronization signal; and c. a source of said resynchronization signal which enables generation of the second clock signal such that the second clock signal is in a determined phase relationship to the master clock signal.
Claim 11
Dependent Claim
43 words
The apparatus of claim 8, wherein the resynchronization signal further enables generation of the second clock signal relative to a test vector pattern in a mixed-signal tester when the second clock signal is in a determined phase relationship to the test vector pattern.
Claim 12
Dependent Claim
28 words
The apparatus of claim 8, wherein the master clock signal source is controllable for generating a digital clock signal at a selected frequency lying within a frequency range.
Claim 13
Dependent Claim
39 words
The apparatus of claim 10, wherein the digital synthesizer is responsive to the master clock signal for generating the second clock signal such that frequency of the second clock signal varies with frequency variation in the master clock signal.
Claim 14
Dependent Claim
36 words
The apparatus of claim 8, further comprising a gate for passing the second clock signal to a clock-generator output at a time interval after generation of the second clock signal is enabled by the resynchronization signal.
Claim 15
Dependent Claim
51 words
The apparatus of claim 8, wherein phase of a test vector pattern is indicated by a trigger signal, and further comprising a counter for counting a number N of clock events following the trigger and a sequencer responsive to the counter for inserting a programmed delay in the test vector pattern.
Claim 16
Dependent Claim
28 words
The apparatus of claim 8, wherein the master clock signal source, the digital synthesizer, and the source of said resynchronization signal, comprise elements of a mixed-signal integrated-circuit tester.
References Cited (Backward Citations)
US4560939A
Cited
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| 3.5 Years (Year 4) | 2000-08-04 | 2001-02-03 | 2001-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-04 | 2005-02-03 | 2005-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-04 | 2009-02-03 | 2009-08-05 | $7700.00 | Window Closed / Lapsed |