Patent US6174754B1 successfully refreshed from Google Patents.
US6174754B1
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Methods for formation of silicon-on-insulator (SOI) and source/drain-on-insulator(SDOI) transistors
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 2000-03-17
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Granted: 2001-01-16
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Expires: 2020-03-17
Abstract
Abstract A method for fabricating a transistor device on a semiconductor substrate, comprising the following steps. A semiconductor substrate having a silicon surface with an overlying insulating dielectric layer is provided. The insulating dielectric layer is patterned to define hole/channel regions having predetermined widths. An amorphous silicon layer is formed having a predetermined thickness over the dielectric layer and the hole/channel regions, filling the hole/channel regions. Heating (grain growth) the amorphous silicon layer to form a planar silicon layer, comprising at least a portion of epitaxial-silicon, having a predetermined thickness, over the dielectric layer and through the hole/channel regions, filling the hole/channel regions. The planar silicon layer is patterned to expose the hole/channel regions and define transistor regions. Trenches are formed in the silicon surface adjacent the transistor regions. Shallow trench isolation regions are formed filling the trenches and having a predetermined depth. Transistor structures are formed within the transistor regions, separated by the shallow trench isolation regions.
Inventors
- 👤 Jin-Yuan Lee
- 👤 Mong-Song Liang
- 👤 Boon-Khim Liew
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 12:56
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/0278; H10D62/00; H10D62/10; H10D62/113; H10D62/115; H10D62/116; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181; H10P90/1912; H10W10/011; H10W10/014; H10W10/17
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
174 words
A method for fabricating a silicon-on-insulator device on a semiconductor substrate, comprising the steps of: providing said semiconductor substrate having a silicon surface with an overlying insulating dielectric layer; patterning said insulating dielectric layer to define hole regions having predetermined widths; forming a silicon layer having a predetermined thickness over said dielectric layer and said hole regions, filling said hole regions; said silicon layer is comprised of amorphous silicon; heating (grain growth) said silicon layer to form a planar epitaxial-silicon layer, having a predetermined thickness, over said dielectric layer and through said hole regions, filling said hole regions; patterning said epitaxial-silicon layer to expose said hole regions and define transistor regions separated by said hole regions; forming trenches in said silicon surface in said hole regions adjacent said epitaxial-silicon layer; forming shallow trench isolation regions filling said trenches and having a predetermined depth within said hole regions; and forming transistor structures within said transistor regions, separated by said shallow trench isolation regions; whereby said transistor structures are on said patterned epitaxial-silicon-on-said insulating dielectric layer.
Claim 2
Independent Claim
174 words
A method for fabricating a silicon-on-insulator device on a semiconductor substrate, comprising the steps of: providing said semiconductor substrate having a silicon surface with an overlying insulating dielectric layer; patterning said insulating dielectric layer to define hole regions having predetermined widths; forming a silicon layer having a predetermined thickness over said dielectric layer and said hole regions, filling said hole regions; said silicon layer is comprised of amorphous silicon; heating (grain growth) said silicon layer to form a planar epitaxial-silicon layer, having a predetermined thickness, over said dielectric layer and through said hole regions, filling said hole regions; patterning said epitaxial-silicon layer to expose said hole regions and define transistor regions separated by said hole regions; forming trenches in said silicon surface in said hole regions adjacent said epitaxial-silicon layer; forming shallow trench isolation regions filling said trenches and having a predetermined depth within said hole regions; and forming transistor structures within said transistor regions, separated by said shallow trench isolation regions; whereby said transistor structures are on said patterned epitaxial-silicon-on-said insulating dielectric layer.
Claim 3
Dependent Claim
23 words
The method of claim 1 , wherein said predetermined thickness of said planar epitaxial-polysilicon layer is from about 500 to 1500 Å thick.
Claim 4
Dependent Claim
18 words
The method of claim 1 , wherein said hole regions are from about 500 to 4000 Å wide.
Claim 5
Dependent Claim
18 words
The method of claim 1 , including the step of forming an interdielectric layer over said transistor structures.
Claim 6
Dependent Claim
19 words
The method of claim 1 , wherein said shallow isolation trenches are from about 1000 to 4000 Å deep.
Claim 7
Dependent Claim
70 words
The method of claim 1 , wherein said patterning of said epitaxial-silicon layer includes the following steps: forming a pad oxide layer over said epitaxial-silicon layer and centered over said patterned dielectric layer; forming a silicon nitride layer over said pad oxide layer; and patterning said pad oxide layer, silicon nitride layer and a portion of said planar epitaxial-silicon layer to expose said hole regions and define said transistor region.
Claim 8
Dependent Claim
59 words
The method of claim 1 , wherein said silicon layer is formed by LPCVD at a temperature less than about 600° C. with a gas selected from the group comprising SH 4 and SiH 2 Cl 2 , with said heating of said silicon layer is performed in a vacuum at a temperature between about 550 to 650° C.
Claim 9
Dependent Claim
34 words
The method of claim 1 , wherein said predetermined thickness of said planar epitaxial-silicon layer is from about 500 to 1500 Å, and said hole regions are from about 500 to 4000 Å wide.
Claim 10
Dependent Claim
31 words
The method of claim 1 , wherein said silicon layer comprises amorphous silicon and said heating of said silicon layer is conducted at a temperature from about 550° to 650° C.
Claim 11
Dependent Claim
91 words
The method of claim 1 , wherein formation of said shallow trench isolation regions comprises the steps of: depositing a pad oxide layer over said epitaxial-silicon layer; depositing a Si 3 N 4 layer over said pad oxide layer; patterning said Si 3 N 4 , pad oxide, epitaxial-silicon layer, and insulating dielectric layers and forming said trenches; depositing oxide in said trenches; planarizing said oxide filled trenches exposing said Si 3 N 4 layer; then removing said Si 3 N 4 and pad oxide layers by a wet chemical treatment.
Claim 12
Dependent Claim
34 words
The method of claim 1 , wherein said transistor structures include: a gate on said transistor region; and source and drain regions on either side of said gate also formed on said transistor region.
Claim 13
Dependent Claim
59 words
The method of claim 1 , wherein said silicon layer is formed by LPCVD at a temperature less than about 600° C. with a gas selected from the group comprising SH 4 and SiH2Cl 2 , with said heating of said silicon layer is performed in an inert gas atmosphere at a temperature between about 550 to 650° C.
Claim 14
Independent Claim
177 words
A method for fabricating a silicon-on-insulator device on a semiconductor substrate, comprising the steps of: providing said semiconductor substrate having a silicon surface with an overlying insulating dielectric layer; patterning said insulating dielectric layer to define hole regions having predetermined widths; forming a silicon layer, having a predetermined thickness of from about 500 to 1500 Å, over said dielectric layer and said hole regions; heating (grain growth) said silicon layer to form a planar epitaxial-silicon layer, having a predetermined thickness, over said dielectric layer and within said hole regions, filling said hole regions; patterning said epitaxial-silicon layer to expose said hole regions and define transistor regions separated by said hole regions; forming shallow trench isolation regions having predetermined depths within said hole regions; and forming transistor structures within said transistor regions, separated by said shallow trench isolation regions, said transistor structures including: a gate on said transistor region; and source and drain regions on either side of said gate also formed on said transistor region; whereby said transistor structures are on said patterned epitaxial-silicon-on-said insulating dielectric layer.
Claim 15
Independent Claim
177 words
A method for fabricating a silicon-on-insulator device on a semiconductor substrate, comprising the steps of: providing said semiconductor substrate having a silicon surface with an overlying insulating dielectric layer; patterning said insulating dielectric layer to define hole regions having predetermined widths; forming a silicon layer, having a predetermined thickness of from about 500 to 1500 Å, over said dielectric layer and said hole regions; heating (grain growth) said silicon layer to form a planar epitaxial-silicon layer, having a predetermined thickness, over said dielectric layer and within said hole regions, filling said hole regions; patterning said epitaxial-silicon layer to expose said hole regions and define transistor regions separated by said hole regions; forming shallow trench isolation regions having predetermined depths within said hole regions; and forming transistor structures within said transistor regions, separated by said shallow trench isolation regions, said transistor structures including: a gate on said transistor region; and source and drain regions on either side of said gate also formed on said transistor region; whereby said transistor structures are on said patterned epitaxial-silicon-on-said insulating dielectric layer.
Claim 16
Dependent Claim
18 words
The method of claim 13 , including the step of forming an interdielectric layer over said transistor structures.
Claim 17
Dependent Claim
34 words
The method of claim 13 , wherein said predetermined thickness of said planar epitaxial-silicon layer is from about 500 to 1500 Å, and said hole regions are from about 500 to 4000 Å wide.
Claim 18
Dependent Claim
74 words
The method of claim 13 , wherein said patterning of said epitaxial-silicon layer includes the following steps: forming a pad oxide layer over said epitaxial-silicon layer and centered over said patterned dielectric layer; forming a Si 3 N 4 layer over said pad oxide layer; and patterning said pad oxide layer, Si 3 N 4 layer and a portion of said planar epitaxial-silicon layer to expose said hole regions and define said transistor region.
Claim 19
Dependent Claim
23 words
The method of claim 13 , wherein said predetermined thickness of said planar epitaxial-polysilicon layer is from about 500 to 1500 Å thick.
Claim 20
Dependent Claim
32 words
The method of claim 13 , wherein said silicon layer comprises amorphous silicon and said heating of said silicon layer is conducted at a temperature of from about 550° to 650° C.
Claim 21
Independent Claim
205 words
A method for fabricating a source/drain-on-insulator device on a semiconductor substrate, comprising the steps of: providing said semiconductor substrate having a silicon surface with an overlying insulating dielectric layer; patterning said insulating dielectric layer to define a channel region, said dielectric layer being divided into left inner and outer portions and right inner and outer portions; forming an amorphous silicon layer, having a predetermined thickness, over said dielectric layer and said channel region; heating (grain growth) said amorphous silicon layer to form planar polysilicon layers, having predetermined widths and thicknesses, over said left and right outer insulating dielectric layer portions and to form a planar epitaxial-silicon layer, having a predetermined width and thickness, over said left and right inner insulating dielectric layer portions and within said channel region, filling said channel region; patterning said polysilicon and epitaxial-silicon layers to define a transistor region; and forming a transistor structure within said transistor region, said transistor structure having: a gate centered on said channel region; and source and drain regions on either side of said gate formed within said planar polysilicon layer and part of said planar epitaxial-silicon layer outward of said channel region; whereby said source and drain regions are on said patterned insulating dielectric layer.
Claim 22
Independent Claim
205 words
A method for fabricating a source/drain-on-insulator device on a semiconductor substrate, comprising the steps of: providing said semiconductor substrate having a silicon surface with an overlying insulating dielectric layer; patterning said insulating dielectric layer to define a channel region, said dielectric layer being divided into left inner and outer portions and right inner and outer portions; forming an amorphous silicon layer, having a predetermined thickness, over said dielectric layer and said channel region; heating (grain growth) said amorphous silicon layer to form planar polysilicon layers, having predetermined widths and thicknesses, over said left and right outer insulating dielectric layer portions and to form a planar epitaxial-silicon layer, having a predetermined width and thickness, over said left and right inner insulating dielectric layer portions and within said channel region, filling said channel region; patterning said polysilicon and epitaxial-silicon layers to define a transistor region; and forming a transistor structure within said transistor region, said transistor structure having: a gate centered on said channel region; and source and drain regions on either side of said gate formed within said planar polysilicon layer and part of said planar epitaxial-silicon layer outward of said channel region; whereby said source and drain regions are on said patterned insulating dielectric layer.
Claim 23
Dependent Claim
22 words
The method of claim 19 , wherein said planar polysilicon and planar epitaxial-silicon layer are from about 500 to 1500 Å thick.
Claim 24
Dependent Claim
18 words
The method of claim 19 , wherein said channel region is from about 500 to 4000 Å wide.
Claim 25
Dependent Claim
18 words
The method of claim 19 , including the step of forming an interdielectric layer over said transistor structure.
Claim 26
Dependent Claim
21 words
The method of claim 19 , including the step of forming shallow isolation trenches on each side of said transistor structure.
Claim 27
Dependent Claim
71 words
The method of claim 19 , wherein said patterning of said polysilicon and epitaxial-silicon layers includes the following steps: forming a pad oxide layer over said polysilicon and epitaxial-silicon layers centered over said channel region; forming a Si 3 N 4 layer over said pad oxide layer; and patterning said pad oxide layer, Si 3 N 4 layer and a portion of said planar polysilicon layer to define said transistor region.
Claim 28
Dependent Claim
32 words
The method of claim 19 , wherein said silicon layer comprises amorphous silicon and said heating of said silicon layer is conducted at a temperature of from about 550° to 650° C.
Claim 29
Independent Claim
219 words
A method for fabricating a source/drain-on-insulator device on a semiconductor substrate, comprising the steps of: providing said semiconductor substrate having a silicon surface with an overlying insulating dielectric layer; patterning said insulating dielectric layer to define a channel region having a width from about 500 to 4000 Å, said dielectric layer being divided into left inner and outer portions and right inner and outer portions; forming a silicon layer, having a predetermined thickness of from about 500 to 1500 Å, over said dielectric layer and said channel region; heating (grain growth) said silicon layer to form planar polysilicon layers, having predetermined widths and thicknesses, over said left and right outer insulating dielectric layer portions and to form a planar epitaxial-silicon layer, having a predetermined width and thickness, over said left and right inner insulating dielectric layer portions and within said channel region, filling said channel region; patterning said polysilicon and epitaxial-silicon layers to define a transistor region; and forming a transistor structure within said transistor region, said transistor structure having: a gate centered on said channel region; and source and drain regions on either side of said gate formed within said planar polysilicon layer and part of said planar epitaxial layer outward of said channel region; whereby said source and drain regions are on said patterned insulating dielectric layer.
Claim 30
Independent Claim
219 words
A method for fabricating a source/drain-on-insulator device on a semiconductor substrate, comprising the steps of: providing said semiconductor substrate having a silicon surface with an overlying insulating dielectric layer; patterning said insulating dielectric layer to define a channel region having a width from about 500 to 4000 Å, said dielectric layer being divided into left inner and outer portions and right inner and outer portions; forming a silicon layer, having a predetermined thickness of from about 500 to 1500 Å, over said dielectric layer and said channel region; heating (grain growth) said silicon layer to form planar polysilicon layers, having predetermined widths and thicknesses, over said left and right outer insulating dielectric layer portions and to form a planar epitaxial-silicon layer, having a predetermined width and thickness, over said left and right inner insulating dielectric layer portions and within said channel region, filling said channel region; patterning said polysilicon and epitaxial-silicon layers to define a transistor region; and forming a transistor structure within said transistor region, said transistor structure having: a gate centered on said channel region; and source and drain regions on either side of said gate formed within said planar polysilicon layer and part of said planar epitaxial layer outward of said channel region; whereby said source and drain regions are on said patterned insulating dielectric layer.
Claim 31
Dependent Claim
18 words
The method of claim 26 , including the step of forming an interdielectric layer over said transistor structure.
Claim 32
Dependent Claim
21 words
The method of claim 26 , including the step of forming shallow isolation trenches on each side of said transistor structure.
Claim 33
Dependent Claim
71 words
The method of claim 26 , wherein said patterning of said polysilicon and epitaxial-silicon layers includes the following steps: forming a pad oxide layer over said polysilicon and epitaxial-silicon layers centered over said channel region; forming a Si 3 N 4 layer over said pad oxide layer; and patterning said pad oxide layer, Si 3 N 4 layer and a portion of said planar olysilicon layer to define said transistor region.
Claim 34
Dependent Claim
32 words
The method of claim 26 , wherein said silicon layer comprises amorphous silicon and said heating of said silicon layer is conducted at a temperature of from about 550° to 650° C.
Claim 35
Independent Claim
151 words
A method for fabricating a transistor device on a semiconductor substrate, comprising the steps of: providing said semiconductor substrate having a silicon surface with an overlying insulating dielectric layer; patterning said insulating dielectric layer to define hole/channel regions having predetermined widths; forming an amorphous silicon layer having a predetermined thickness over said dielectric layer and said hole/channel regions, filling said hole/channel regions; heating (grain growth) said amorphous silicon layer to form a planar silicon layer, comprising at least a portion of epitaxial-silicon, having a predetermined thickness, over said dielectric layer and through said hole/channel regions, filling said hole/channel regions; patterning said planar silicon layer to expose said hole/channel regions and define transistor regions; forming trenches in said silicon surface adjacent said transistor regions; forming shallow trench isolation regions filling said trenches and having a predetermined depth; and forming transistor structures within said transistor regions, separated by said shallow trench isolation regions.
Claim 36
Independent Claim
151 words
A method for fabricating a transistor device on a semiconductor substrate, comprising the steps of: providing said semiconductor substrate having a silicon surface with an overlying insulating dielectric layer; patterning said insulating dielectric layer to define hole/channel regions having predetermined widths; forming an amorphous silicon layer having a predetermined thickness over said dielectric layer and said hole/channel regions, filling said hole/channel regions; heating (grain growth) said amorphous silicon layer to form a planar silicon layer, comprising at least a portion of epitaxial-silicon, having a predetermined thickness, over said dielectric layer and through said hole/channel regions, filling said hole/channel regions; patterning said planar silicon layer to expose said hole/channel regions and define transistor regions; forming trenches in said silicon surface adjacent said transistor regions; forming shallow trench isolation regions filling said trenches and having a predetermined depth; and forming transistor structures within said transistor regions, separated by said shallow trench isolation regions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2004-01-16 | 2004-07-17 | 2005-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-16 | 2008-07-17 | 2009-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-16 | 2012-07-17 | 2013-01-16 | $7700.00 | Window Closed / Lapsed |