US6169325B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device
Assignee: Longitude Licensing Ltd
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Filing: 1998-12-15
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Granted: 2001-01-02
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Expires: 2018-12-15
Abstract
Abstract To realize low-profile electronic apparatus (a memory module and a memory card) of a large storage size by mounting tape carrier packages (TCPs) with a memory chip encapsulated onto a wiring board in high density. To be more specific, a TCP is composed of an insulating tape, leads formed on one side thereof, a potting resin with a semiconductor chip encapsulated, and a pair of support leads arranged on two opposite short sides. The pair of support leads function to hold the TCP at a constant tilt angle relative to the mounting surface of the wiring board. By varying the length vertical to the mounting surface, the TCP can be mounted to a desired tilt angle.
Inventors
- 👤 Shuichiro Azuma
- 👤 Takayuki Okinaga
- 👤 Takashi Emata
- 👤 Tomoaki Kudaishi
- 👤 Tamaki Wada
- 👤 Kunihiko Nishi
- 👤 Masachika Masuda
- 👤 Toshio Sugano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:30
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/30; H05K3/303; H10; H10W; H10W74/00; H10W90/00; H05K2201/00; H05K2201/09; H05K2201/09209; H05K2201/09654; H05K2201/09781; H05K2201/10; H05K2201/10431; H05K2201/10439; H05K2201/10462; H05K2201/10484; H05K2201/10568; H05K2201/10613; H05K2201/10621; H05K2201/10681; H05K2201/10742; H05K2201/1075; H05K2201/1078; H05K2201/20; H05K2201/2036; H10W70/00; H10W70/40; H10W70/60; Y; Y02; Y02P; Y02P70/00; Y02P70/50
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
324 words
A semiconductor device comprising: a wiring board having a plurality of wiring layers and a plurality of terminals connected to said plurality of wiring layers; and a plurality of semiconductor packages mounted on said wiring board; each of said plurality of semiconductor packages having an insulating tape rectangular in shape having a device hole, a semiconductor chip rectangular in shape formed on a main surface thereof with an integrated circuit and a plurality of bonding pads, said semiconductor chip being arranged in said device hole of said insulating tape, a plurality of first leads formed on one surface of said insulating tape, each of said plurality of first leads having a first portion extending over said main surface of said semiconductor chip and a second portion formed integrally with said first portion and projecting from one long side of said insulating tape to outside, an end of said first portion being electrically connected to corresponding one of said plurality of bonding pads of said semiconductor chip, a support lead formed on one surface of said insulating tape and projecting from a short side of said insulating tape outside, and a resin layer for encapsulating said main surface of said semiconductor chip and said first portion of said first lead; wherein a tip of said second portion of said first lead of each of said plurality of semiconductor packages is connected to corresponding one of said plurality of terminals of said wiring board, the tip of said support lead of each of said plurality of semiconductor packages comes in contact with said wiring board, each of said plurality of semiconductor packages is mounted on said wiring board with a predetermined tilt angle defined by the length of said support lead in a thickness direction of said wiring board, and said plurality of semiconductor packages are arranged in a predetermined direction, each of said plurality of semiconductor packages partially overlapping adjacent ones in a planar manner.
Claim 2
Dependent Claim
324 words
A semiconductor device comprising: a wiring board having a plurality of wiring layers and a plurality of terminals connected to said plurality of wiring layers; and a plurality of semiconductor packages mounted on said wiring board; each of said plurality of semiconductor packages having an insulating tape rectangular in shape having a device hole, a semiconductor chip rectangular in shape formed on a main surface thereof with an integrated circuit and a plurality of bonding pads, said semiconductor chip being arranged in said device hole of said insulating tape, a plurality of first leads formed on one surface of said insulating tape, each of said plurality of first leads having a first portion extending over said main surface of said semiconductor chip and a second portion formed integrally with said first portion and projecting from one long side of said insulating tape to outside, an end of said first portion being electrically connected to corresponding one of said plurality of bonding pads of said semiconductor chip, a support lead formed on one surface of said insulating tape and projecting from a short side of said insulating tape outside, and a resin layer for encapsulating said main surface of said semiconductor chip and said first portion of said first lead; wherein a tip of said second portion of said first lead of each of said plurality of semiconductor packages is connected to corresponding one of said plurality of terminals of said wiring board, the tip of said support lead of each of said plurality of semiconductor packages comes in contact with said wiring board, each of said plurality of semiconductor packages is mounted on said wiring board with a predetermined tilt angle defined by the length of said support lead in a thickness direction of said wiring board, and said plurality of semiconductor packages are arranged in a predetermined direction, each of said plurality of semiconductor packages partially overlapping adjacent ones in a planar manner.
Claim 3
Dependent Claim
19 words
The semiconductor device according to claim 1 , wherein said predetermined tilt angle is not more than 45 degrees.
Claim 4
Dependent Claim
26 words
The semiconductor device according to claim 1 , wherein the adjacent semiconductor packages are arranged with a predetermined interval in an area of the planar overlapping.
Claim 5
Dependent Claim
48 words
The semiconductor device according to claim 1 , wherein said second portion of said first lead of each of said plurality of semiconductor packages has a bent between said tip connected to said corresponding one of said plurality of terminals of said wiring board and said insulating tape.
Claim 6
Dependent Claim
30 words
The semiconductor device according to claim 1 , wherein a rear surface of said semiconductor chip of each of said plurality of semiconductor packages is exposed from said resin layer.
Claim 7
Dependent Claim
67 words
The semiconductor device according to claim 1 , wherein a third portion is provided between said first portion and said second portion of said first lead of each of said plurality of semiconductor packages, said third portion being wider than said first portion and said second portion, a rim portion of said resin layer being positioned in the proximity of said third portion of said first lead.
Claim 8
Dependent Claim
458 words
A semiconductor device comprising: a wiring board rectangular in shape having a plurality of wiring layers and a plurality of terminals connected to said plurality of wiring layers, said wiring board having a pair of long sides extending in a first direction and a pair of short sides extending in a second direction different from said first direction; a plurality of first semiconductor packages mounted on said wiring board; and a plurality of second semiconductor packages mounted on said wiring board; each of said plurality of first semiconductor packages and said plurality of second semiconductor packages having an insulating tape rectangular in shape having a device hole, a semiconductor chip rectangular in shape formed on a main surface thereof with an integrated circuit and a plurality of bonding pads, said semiconductor chip being arranged in said device hole of said insulating tape, a plurality of first leads formed on one surface of said insulating tape, each of said plurality of first leads having a first portion extending over said main surface of said semiconductor chip and a second portion formed integrally with said first portion and projecting from one long side of said insulating tape to outside, an end of said first portion being electrically connected to corresponding one of said plurality of bonding pads of said semiconductor chip, a support lead formed on one surface of said insulating tape and projecting from a short side of said insulating tape outside, and a resin layer for encapsulating said main surface of said semiconductor chip and said first portion of said first lead; wherein a tip of said second portion of said first lead of each of said plurality of first semiconductor packages and said plurality of second semiconductor packages is connected to corresponding one of said plurality of terminals of said wiring board, the tip of said support lead of each of said plurality of first semiconductor packages and said plurality of second semiconductor packages comes in contact with said wiring board, each of said plurality of first semiconductor packages and said plurality of second semiconductor packages is mounted on said wiring board with a predetermined tilt angle defined by the length of said support lead in a thickness direction of said wiring board, said plurality of first semiconductor packages are arranged from one long side of said wiring board along said second direction, the adjacent semiconductor packages overlapping each other in a planar manner, said plurality of second semiconductor packages are arranged from the other long side of said wiring board along said second direction, the adjacent semiconductor packages overlapping each other in a planar manner, and said plurality of first semiconductor packages and said plurality of second semiconductor packages are adjacently arranged in said first direction.
Claim 9
Dependent Claim
458 words
A semiconductor device comprising: a wiring board rectangular in shape having a plurality of wiring layers and a plurality of terminals connected to said plurality of wiring layers, said wiring board having a pair of long sides extending in a first direction and a pair of short sides extending in a second direction different from said first direction; a plurality of first semiconductor packages mounted on said wiring board; and a plurality of second semiconductor packages mounted on said wiring board; each of said plurality of first semiconductor packages and said plurality of second semiconductor packages having an insulating tape rectangular in shape having a device hole, a semiconductor chip rectangular in shape formed on a main surface thereof with an integrated circuit and a plurality of bonding pads, said semiconductor chip being arranged in said device hole of said insulating tape, a plurality of first leads formed on one surface of said insulating tape, each of said plurality of first leads having a first portion extending over said main surface of said semiconductor chip and a second portion formed integrally with said first portion and projecting from one long side of said insulating tape to outside, an end of said first portion being electrically connected to corresponding one of said plurality of bonding pads of said semiconductor chip, a support lead formed on one surface of said insulating tape and projecting from a short side of said insulating tape outside, and a resin layer for encapsulating said main surface of said semiconductor chip and said first portion of said first lead; wherein a tip of said second portion of said first lead of each of said plurality of first semiconductor packages and said plurality of second semiconductor packages is connected to corresponding one of said plurality of terminals of said wiring board, the tip of said support lead of each of said plurality of first semiconductor packages and said plurality of second semiconductor packages comes in contact with said wiring board, each of said plurality of first semiconductor packages and said plurality of second semiconductor packages is mounted on said wiring board with a predetermined tilt angle defined by the length of said support lead in a thickness direction of said wiring board, said plurality of first semiconductor packages are arranged from one long side of said wiring board along said second direction, the adjacent semiconductor packages overlapping each other in a planar manner, said plurality of second semiconductor packages are arranged from the other long side of said wiring board along said second direction, the adjacent semiconductor packages overlapping each other in a planar manner, and said plurality of first semiconductor packages and said plurality of second semiconductor packages are adjacently arranged in said first direction.
Claim 10
Dependent Claim
19 words
The semiconductor device according to claim 7 , wherein said predetermined tilt angle is not more than 45 degrees.
Claim 11
Dependent Claim
25 words
The semiconductor device according to claim 7 , wherein said adjacent packages are arranged with a predetermined interval in an area of the planar overlapping.
Claim 12
Dependent Claim
56 words
The semiconductor device according to claim 7 , wherein said second portion of said first lead of each of said plurality of first semiconductor packages and said plurality of second semiconductor packages has a bent between said tip connected to said corresponding one of said plurality of terminals of said wiring board and said insulating tape.
Claim 13
Dependent Claim
38 words
The semiconductor device according to claim 7 , wherein a rear surface of said semiconductor chip of each of said plurality of first semiconductor packages and said plurality of second semiconductor packages is exposed from said resin layer.
Claim 14
Dependent Claim
75 words
The semiconductor device according to claim 7 , wherein a third portion is provided between said first portion and said second portion of said first lead of each of said plurality of first semiconductor packages and said plurality of second semiconductor packages, said third portion being wider than said first portion and said second portion, a rim portion of said resin layer being positioned in the proximity of said third portion of said first lead.
References Cited (Backward Citations)
US5396102A
Cited
US5103247A
Cited
US4984064A
Cited
US5227664A
Cited
USRE36325E
Cited
US5057907A
Cited
JPH0465135A
Cited
EP0531724A1
Cited
US5239447A
Cited
EP0575806A2
Cited
US5661339A
Cited
US5731633A
Cited
US6049975A
Cited
JPH07321441A
Cited
JPH08191127A
Cited
US5973404A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-02 | 2004-07-03 | 2005-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-02 | 2008-07-03 | 2009-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-02 | 2012-07-03 | 2013-01-02 | $7700.00 | Window Closed / Lapsed |