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Patent US6168891B1 successfully refreshed from Google Patents.
US6168891B1
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Method for correcting mask pattern for use in manufacturing of semiconductor integrated circuit
Assignee: Socionext Inc
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Filing: 1999-11-29
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Granted: 2001-01-02
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Expires: 2019-11-29
Abstract
Abstract A method for correcting a mask pattern for use in manufacturing of a semiconductor integrated circuit according to the invention comprises the steps of: sorting pattern units which compose a mask pattern, based on their respective shape and/or relative positional relationship with adjacent pattern units; selectively performing pattern correction on some of the pattern units which have been sorted out at the sorting step.
Inventors
- 👤 Hidenori Shibata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 23:42
CPC Classifications
G; G03; G03F; G03F7/00; G03F7/70; G03F7/70425; G03F7/70433; G03F7/70441; G03F1/00; G03F1/36
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
170 words
A method for correcting a mask pattern for use in manufacturing of a semiconductor integrated circuit, which comprises the steps of: sorting pattern units based on a shape and/or a relative positional relationship with a proximate pattern unit of said pattern units which includes said mask pattern; performing pattern correction on pattern units selected from among said pattern units sorted at said sorting step; said sorting step is a step for sorting out said pattern units as correction-subject units and subject units; said correction step is a step for selectively performing pattern correction on said pattern units sorted out as said correction-subject units at said sorting step; said sorting step is a step for further sorting pattern units sorted out as said correction-subject units, into groups suited for a plurality of pattern correction types respectively; and said correction step is a step for performing an optimal pattern correction on said correction-subject units which are sorted into said groups suited for said plurality of pattern correction types by said sorting step.
Claim 2
Independent Claim
170 words
A method for correcting a mask pattern for use in manufacturing of a semiconductor integrated circuit, which comprises the steps of: sorting pattern units based on a shape and/or a relative positional relationship with a proximate pattern unit of said pattern units which includes said mask pattern; performing pattern correction on pattern units selected from among said pattern units sorted at said sorting step; said sorting step is a step for sorting out said pattern units as correction-subject units and subject units; said correction step is a step for selectively performing pattern correction on said pattern units sorted out as said correction-subject units at said sorting step; said sorting step is a step for further sorting pattern units sorted out as said correction-subject units, into groups suited for a plurality of pattern correction types respectively; and said correction step is a step for performing an optimal pattern correction on said correction-subject units which are sorted into said groups suited for said plurality of pattern correction types by said sorting step.
Claim 3
Dependent Claim
49 words
The method for correcting a mask pattern for use in manufacturing of a semiconductor integrated circuit according to claim 1 , wherein said sorting step is a step for sorting said correction-subject units as said correction-subject units and said subject units based on a width of said pattern units.
Claim 4
Dependent Claim
49 words
The method for correcting a mask pattern for use in manufacturing of a semiconductor integrated circuit according to claim 2 , wherein said sorting step is a step for sorting pattern units, of said pattern units, that have a width smaller than a predetermined value, as said correction-subject units.
Claim 5
Dependent Claim
50 words
The method for correcting a mask pattern for use in manufacturing of a semiconductor integrated circuit according to claim 1 , wherein said sorting step is a step for sorting said pattern units into said correction-subject units and said subject units based on a distance between mutually proximate pattern units.
Claim 6
Dependent Claim
53 words
The method for correcting a mask pattern for use in manufacturing of a semiconductor integrated circuit according to claim 4 , wherein said sorting step is a step for pattern units, of said pattern units, that have a distance with a proximate pattern unit smaller than a predetermined value, as said correction-subject units.
Claim 7
Dependent Claim
44 words
The method for correcting a mask pattern for use in manufacturing of a semiconductor integrated circuit according to claim 1 , wherein said sorting step is a step for sorting said correction-subject units into said groups based on a width of said correction-subject units.
Claim 8
Dependent Claim
49 words
The method for correcting a mask pattern for use in manufacturing of a semiconductor integrated circuit according to claim 1 , wherein said sorting step is a step for sorting said correction-subject units into said groups based on a distance between said correction-subject units and a proximate pattern unit.
Claim 9
Dependent Claim
29 words
The method for correcting a mask pattern for use in manufacturing of a semiconductor integrated circuit according to claim 1 , where pattern correction is optical proximity effect correction.
Claim 10
Dependent Claim
44 words
The method for correcting a mask pattern for use in manufacturing of a semiconductor integrated circuit according to claim 1 , wherein said plurality of pattern correction methods are a simulation-based optical proximity effect correction method and a rule-based optical proximity effect correction method.
Claim 11
Independent Claim
161 words
A method for correcting a mask pattern for use in manufacturing of a semiconductor integrated circuit, which comprises the steps of: sorting sides which are elements that compose each of pattern units which compose a mask pattern, based on a shape and/or a relative positional relationship of said side with a proximate side; selectively performing pattern correction on said sides sorted at said sorting step; said sorting step is a step for sorting out said sides as correction-subject units and subject units; said correction step is a step for selectively performing pattern correction on sides which are sorted as correction-subject sides at said sorting step; said sorting step is a step for further sorting pattern units sorted out as said correction-subject units, into groups suited for a plurality of types of pattern correction; and said correction step is a step for performing optimal pattern correction on said correction-subject units sorted into said groups of said plurality of types of pattern correction.
Claim 12
Independent Claim
161 words
A method for correcting a mask pattern for use in manufacturing of a semiconductor integrated circuit, which comprises the steps of: sorting sides which are elements that compose each of pattern units which compose a mask pattern, based on a shape and/or a relative positional relationship of said side with a proximate side; selectively performing pattern correction on said sides sorted at said sorting step; said sorting step is a step for sorting out said sides as correction-subject units and subject units; said correction step is a step for selectively performing pattern correction on sides which are sorted as correction-subject sides at said sorting step; said sorting step is a step for further sorting pattern units sorted out as said correction-subject units, into groups suited for a plurality of types of pattern correction; and said correction step is a step for performing optimal pattern correction on said correction-subject units sorted into said groups of said plurality of types of pattern correction.
Claim 13
Dependent Claim
60 words
The method for correcting a mask pattern for use in manufacturing of a semiconductor integrated circuit according to claim 10 , wherein said sorting step is a step for sorting out sides as said correction-subject sides and said subject sides based on a length of said sides and an angle of a unit vertex at both ends of said sides.
Claim 14
Dependent Claim
65 words
The method for correcting a mask pattern for use in manufacturing of a semiconductor integrated circuit according to claim 10 , wherein said sorting step is a step for sorting out, as said correction-subject sides, said sides that a length smaller than a predetermined value and also that has an angle of 90 or 270 degrees of units vertices at both ends of said sides.
Claim 15
Dependent Claim
56 words
The method for correcting a mask pattern for use in manufacturing of a semiconductor integrated circuit according to claim 10 , wherein said sorting step is a step for sorting out sides as said correction-subject sides and said subject sides based on a distance between adjacent sides and a length actually opposing between mutually proximate sides.
Claim 16
Dependent Claim
54 words
The method for correcting a mask pattern for use in manufacturing of a semiconductor integrated circuit according to claim 13 , wherein said sorting step is a step for sorting out, as said correction-subject sides, sides that has said distance smaller than a predetermined value and said opposing length larger than another predetermined value.
Claim 17
Dependent Claim
44 words
The method for correcting a mask pattern for use in manufacturing of a semiconductor integrated circuit according to claim 13 , wherein said sorting step is a step for sorting said correction-subject sides into said groups based on a length of said correction-subject sides.
Claim 18
Dependent Claim
51 words
The method for correcting a mask pattern for use in manufacturing of a semiconductor integrated circuit according to claim 13 , wherein said sorting step is a step for sorting said correction-subject units into said groups based on a distance between adjacent sides and a length actually opposing between adjacent sides.
Claim 19
Dependent Claim
30 words
The method for correcting a mask pattern for use in manufacturing of a semiconductor integrated circuit according to claim 10 , wherein said pattern correction is optical proximity effect correction.
Claim 20
Dependent Claim
44 words
The method for correcting a mask pattern for use in manufacturing of a semiconductor integrated circuit according to claim 10 , wherein said plurality of pattern correction methods are a simulation-based optical proximity effect correction method and a rule-based optical proximity effect correction method.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-02 | 2004-07-03 | 2005-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-02 | 2008-07-03 | 2009-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-02 | 2012-07-03 | 2013-01-02 | $7700.00 | Window Closed / Lapsed |