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US6166441A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of forming a via overlap

Assignee: Intel Corp
•
Filing: 1998-11-12
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Granted: 2000-12-26
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Expires: 2018-11-12
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Abstract

Abstract Briefly, in accordance with one embodiment of the invention a method of forming at least two vias, each having a metal overlap, to interconnect at least two connection points with metallization includes the following. The at least two vias are etched through a layer of insulating material. The at least two etched vias are located diagonally with respect to one another. Metal overlap for each of the at least two vias is formed into a polygon shape having more than four sides. Briefly, in accordance with another embodiment of the invention, an article includes: a storage medium, the storage medium having stored thereon, instructions, which, when executed, result in: the placement and routing of vias between at least two connection points to be interconnected with metallization by positioning at least two vias diagonally with respect to one another, the at least two vias being positioned so each is capable of having a polygon shape of metal overlap with more than four sides. Briefly, in accordance with still another embodiment of the invention, an integrated cicuit includes: a semiconductor substrate, the semiconductor substrate having formed thereon an interconnect. The interconnect including at least two vias, the at least two vias being located diagonally with respect to one another and each having a metal overlap with a polygon shape of more than four sides.

Inventors

  • 👤 Nathan Geryk

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 10:55
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/42

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 50 words
An integrated circuit comprising: a semiconductor substrate; said semiconductor substrate having formed thereon an interconnect; said interconnect including at least two vias, said at least two vias being located diagonally with respect to one another and each having a metal overlap with a polygon shape of more than four sides.
Claim 2
Dependent Claim 50 words
An integrated circuit comprising: a semiconductor substrate; said semiconductor substrate having formed thereon an interconnect; said interconnect including at least two vias, said at least two vias being located diagonally with respect to one another and each having a metal overlap with a polygon shape of more than four sides.
Claim 3
Dependent Claim 14 words
The integrated circuit of claim 1, wherein the polygon shape comprises an octagon shape.
Claim 4
Dependent Claim 29 words
The integrated circuit of claim 2, and wherein the location of the at least two vias prior to etching was positioned using an automatic placement and routing (APR) tool.
Claim 5
Dependent Claim 46 words
The integrated circuit of claim 2, wherein the at least two vias are located on a grid with respect to one another, the horizontal and vertical distances between the centers of the at least two vias being in the range of approximately 1 to 2 microns.

References Cited (Backward Citations)

US4196443A Cited
US4951101A Cited
US5508564A Cited
US5432381A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-12-26 2004-06-26 2004-12-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-12-26 2008-06-26 2008-12-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-12-26 2012-06-26 2012-12-26 $7700.00 Window Closed / Lapsed

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