Semiconductor device having an improved packing density and high reliability

Claim 2

A semiconductor device having contact holes selectively formed thereon comprising: a semiconductor substrate; two first impurity diffusion regions of said semiconductor substrate which are positioned on either side of an isolator formed on said semiconductor substrate; and an interlayer insulator having two contact holes formed on a portion of said two first impurity diffusion regions and said interlayer insulator being formed on said two first impurity diffusion regions and on said isolator, wherein said two contact holes are disposed to be offset such that no horizontal axis, defined as the shortest path across the isolator and travelling between the two first impurity diffusion regions, can be drawn connecting the centers of said first and second contact holes, wherein a longest distance across the isolator is below 2 μm, a longest distance between an edge of a contact hole nearest said isolator and said isolator is below 1 μm, and a longest distance between centers of said contact holes is below 5 μm.

Claim 3

The semiconductor device of claim 1, wherein said semiconductor substrate is of a first conductivity type and said impurity diffusion regions formed therein are of a second conductivity type.

Claim 4

The semiconductor device of claim 2, further comprising two second impurity diffusion regions formed by doping, through said corresponding contact holes, second conductivity type impurity ions into said first impurity diffusion regions, respectively.

Claim 5

The semiconductor device of claim 3, wherein said second impurity diffusion regions are formed deeper in said substrate than the corresponding first impurity diffusion regions.

Claim 6

The semiconductor device of claim 1, wherein said isolator is a field oxide layer defining an active region and a device isolating region on said semiconductor substrate.

Claim 7

The semiconductor device of claim 1, wherein said isolator is a gate electrode of a MOS transistor.

Claim 8

The semiconductor device of claim 3, wherein a minimum distance between said two second impurity diffusion regions is at least as long as a minimum width of said isolator.

Claim 9

The semiconductor device of claim 4, wherein a depth of said two first impurity diffusion regions in said substrate is between about 1000 Å and 4000 Å, and a depth of said two second impurity diffusion regions is between about 2000 Å and 5000 Å.

Claim 10

A semiconductor device having contact holes selectively formed thereon comprising: a semiconductor substrate; two first impurity diffusion regions of said semiconductor substrate which are positioned on either side of an isolator formed on said semiconductor substrate, wherein said two first impurity regions are a source region and a drain region, respectively, of a MOS transistor; and an interlayer insulator having two contact holes formed on a portion of said two first impurity diffusion regions and said interlayer insulator being formed on said two first impurity diffusion regions and on said isolator, wherein said two contact holes are disposed to be offset such that no horizontal axis, defined as the shortest path across the isolator and travelling between the two first impurity diffusion regions, can be drawn connecting the centers of said first and second contact holes, wherein a longest distance across the isolator is below 2 μm, a longest distance between an edge of a contact hole nearest said isolator and said isolator is below 1 μm, and a longest distance between centers of said contact holes is below 5 μm.

Claim 11

A semiconductor device having contact holes selectively formed thereon comprising: a semiconductor substrate; two first impurity diffusion regions of said semiconductor substrate which are positioned on either side of an isolator formed on said semiconductor substrate, wherein said two first impurity regions are a source region and a drain region, respectively, of a MOS transistor; and an interlayer insulator having two contact holes formed on a portion of said two first impurity diffusion regions and said interlayer insulator being formed on said two first impurity diffusion regions and on said isolator, wherein said two contact holes are disposed to be offset such that no horizontal axis, defined as the shortest path across the isolator and travelling between the two first impurity diffusion regions, can be drawn connecting the centers of said first and second contact holes, wherein a longest distance across the isolator is below 2 μm, a longest distance between an edge of a contact hole nearest said isolator and said isolator is below 1 μm, and a longest distance between centers of said contact holes is below 5 μm.

Claim 12

The semiconductor device of claim 9, wherein said isolator is a field oxide layer defining an active region and a device isolating region on said substrate.

Claim 13

The semiconductor device of claim 9, wherein said isolator is a gate electrode in said MOS transistor.

Claim 14

The semiconductor device of claim 9, wherein said semiconductor substrate is of a first conductivity type and said first impurity diffusion regions formed therein are of a second conductivity type.

Claim 15

The semiconductor device of claim 12, further comprising two second impurity-doped diffusion regions formed by doping second conductivity type impurity ions into said first impurity diffusion regions through said corresponding contact holes.

Claim 16

The semiconductor device of claim 13, wherein said second impurity diffusion regions extend deeper into said substrate than corresponding said first impurity diffusion regions.

Claim 17

The semiconductor device of claim 9, wherein a minimum distance between said two second impurity diffusion regions is at least as long as a minimum width of said isolator.

Claim 18

The semiconductor device of claim 14, wherein a depth of said two first impurity diffusion regions in said substrate is between about 1000 Å and 4000 Å, and a depth of said two second impurity diffusion regions is between about 2000 Å and 5000 Å.