US6165906A
Expired / Lapsed
US
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Semiconductor topography employing a shallow trench isolation structure with an improved trench edge
Assignee: Advanced Micro Devices Inc
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Filing: 1999-01-26
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Granted: 2000-12-26
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Expires: 2019-01-26
Abstract
Abstract A method of forming an improved isolation trench between active regions within the semiconductor substrate involves oxidizing unmasked portions of a semiconductor substrate prior to etching an isolation trench into the semiconductor substrate. By oxidizing the unmasked portions of the semiconductor prior to etching, an isolation trench with rounded corners may be formed.
Inventors
- 👤 Basab Bandyopadhyay
- 👤 Douglas J. Bonser
- 👤 Michael J. McBride
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:25
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/10; H10W10/17; H10W10/01; H10W10/011; H10W10/014; H10W10/0145; H10W10/0147; H10P; H10P14/00; H10P14/60; H10P14/61; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10P14/6309; H10P14/6322; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/66; H10P14/668; H10P14/6681; H10P14/6684; H10P14/6686; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10P14/694; H10P14/6943; H10P14/69433; H10P50/00; H10P50/20; H10P50/24; H10P50/242; H10P50/28; H10P50/282; H10P50/283
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
117 words
A method for forming an isolation trench comprising: forming a masking layer upon a semiconductor substrate, wherein a window is formed through the masking layer, and wherein the boundaries of the isolation trench are defined by the window; oxidizing an upper surface of the semiconductor substrate, wherein the upper surface of a region of the semiconductor substrate defined by the window is oxidized at a greater rate than regions of the semiconductor substrate covered by the masking layer; and forming the isolation trench within the portion of the semiconductor substrate defined by the window, wherein the semiconductor substrate is substantially rounded at a transition region between the isolation trench and the unetched regions of the semiconductor substrate.
Claim 2
Independent Claim
117 words
A method for forming an isolation trench comprising: forming a masking layer upon a semiconductor substrate, wherein a window is formed through the masking layer, and wherein the boundaries of the isolation trench are defined by the window; oxidizing an upper surface of the semiconductor substrate, wherein the upper surface of a region of the semiconductor substrate defined by the window is oxidized at a greater rate than regions of the semiconductor substrate covered by the masking layer; and forming the isolation trench within the portion of the semiconductor substrate defined by the window, wherein the semiconductor substrate is substantially rounded at a transition region between the isolation trench and the unetched regions of the semiconductor substrate.
Claim 3
Dependent Claim
19 words
The method of claim 1, wherein the masking layer comprises patterned silicon nitride formed upon a pad oxide layer.
Claim 4
Dependent Claim
18 words
The method of claim 2, wherein the pad oxide layer is formed by chemical vapor depositing silicon dioxide.
Claim 5
Dependent Claim
18 words
The method of claim 3, wherein the pad oxide layer is formed by thermally oxidizing the semiconductor substrate.
Claim 6
Dependent Claim
28 words
The method of claim 3, wherein forming the isolation trench comprises: anisotropically etching through the oxidized portion of the semiconductor substrate; and anisotropically etching the underlying semiconductor substrate.
Claim 7
Dependent Claim
30 words
The method of claim 1, wherein the length of time of the oxidation process is varied to vary the degree of rounding of the semiconductor substrate at the transition regions.
Claim 8
Dependent Claim
27 words
The method of claim 1, wherein forming the isolation trench comprises anisotropically etching the semiconductor substrate, wherein the sidewalls of the formed isolation trench are substantially vertical.
Claim 9
Dependent Claim
44 words
The method of claim 1, further comprising: forming sidewalls and a trench floor of the isolation trench by subjecting the isolation trench to an etching process; and oxidizing the sidewalls and the trench floor of the isolation trench to form a dielectric liner layer.
Claim 10
Dependent Claim
43 words
The method of claim 1, further comprising: filling the isolation trench with a dielectric fill layer; planarizing the dielectric fill layer such that an upper surface of the dielectric fill layer is substantially co-planar with an upper surface of the silicon nitride layer.
Claim 11
Dependent Claim
18 words
The method of claim 9, wherein said dielectric fill layer comprises CVD oxide formed from a TEOS source.
Claim 12
Dependent Claim
36 words
The method of claim 9, further comprising: removing the masking layer; and planarizing the dielectric fill such that an upper surface of the dielectric fill layer is co-planar with an upper surface of the semiconductor substrate.
Claim 13
Independent Claim
160 words
A method for forming an isolation trench comprising: forming a dielectric layer upon a semiconductor substrate; forming a masking layer upon the dielectric layer, wherein a window is formed vertically through the masking layer, and wherein the boundaries of the isolation trench are defined by the window; oxidizing the upper surface of the semiconductor substrate, wherein the upper surface of the semiconductor substrate defined by the window is oxidized at a greater rate than portions of the semiconductor substrate covered by the masking layer; and forming the isolation trench within the portion of the semiconductor substrate defined by the window, wherein the semiconductor substrate is substantially rounded at the transition region between the isolation trench and the unetched regions of the semiconductor substrate; filling the isolation trench with a dielectric fill layer; and planarizing the dielectric fill layer such that an upper surface of the dielectric fill layer is substantially co-planar with an upper surface of the silicon nitride layer.
Claim 14
Independent Claim
160 words
A method for forming an isolation trench comprising: forming a dielectric layer upon a semiconductor substrate; forming a masking layer upon the dielectric layer, wherein a window is formed vertically through the masking layer, and wherein the boundaries of the isolation trench are defined by the window; oxidizing the upper surface of the semiconductor substrate, wherein the upper surface of the semiconductor substrate defined by the window is oxidized at a greater rate than portions of the semiconductor substrate covered by the masking layer; and forming the isolation trench within the portion of the semiconductor substrate defined by the window, wherein the semiconductor substrate is substantially rounded at the transition region between the isolation trench and the unetched regions of the semiconductor substrate; filling the isolation trench with a dielectric fill layer; and planarizing the dielectric fill layer such that an upper surface of the dielectric fill layer is substantially co-planar with an upper surface of the silicon nitride layer.
Claim 15
Dependent Claim
17 words
The method of claim 12, wherein the dielectric layer is formed by chemical vapor depositing silicon dioxide.
Claim 16
Dependent Claim
17 words
The method of claim 12, wherein the dielectric layer is formed by thermally oxidizing the semiconductor substrate.
Claim 17
Dependent Claim
30 words
The method of claim 12, wherein the length of time of the oxidation process is varied to vary the degree of rounding of the semiconductor substrate at the transition regions.
Claim 18
Dependent Claim
27 words
The method of claim 12, wherein forming the isolation trench comprises anisotropically etching the semiconductor substrate, wherein the sidewalls of the formed isolation trench are substantially vertical.
Claim 19
Dependent Claim
32 words
The method of claim 12, wherein forming the isolation trench comprises: anisotropically etching through the dielectric layer and the oxidized portion of the semiconductor substrate; and anisotropically etching the underlying semiconductor substrate.
Claim 20
Dependent Claim
44 words
The method of claim 12, further comprising: cleaning sidewalls and a trench floor of the isolation trench by subjecting the isolation trench to an etching process; and oxidizing the sidewalls and the trench floor of the isolation trench to form a dielectric liner layer.
Claim 21
Dependent Claim
18 words
The method of claim 12, wherein the dielectric fill layer comprises CVD oxide formed from a TEOS source.
Claim 22
Dependent Claim
36 words
The method of claim 12, further comprising: removing the masking layer; and planarizing the dielectric fill such that an upper surface of the dielectric fill layer is co-planar with an upper surface of the dielectric layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-12-26 | 2004-06-26 | 2004-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-12-26 | 2008-06-26 | 2008-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-12-26 | 2012-06-26 | 2012-12-26 | $7700.00 | Window Closed / Lapsed |