Patent US6165846A successfully refreshed from Google Patents.
US6165846A
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Method of eliminating gate leakage in nitrogen annealed oxides
Assignee: IXYS Intl Ltd
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Filing: 1999-03-02
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Granted: 2000-12-26
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Expires: 2019-03-02
Abstract
Abstract The improvement of thin tunnel oxides used in EEPROM and FLASH tecnologies using post-oxidation annealing in nitrogen causes defects in subsequent oxide films. These are manifested by oxide thinning at the bird's beak and result in high gate leakage. As the time and temperature to the post-oxidation annealing are increased for improved tunnel oxide performance, the number of defects increases rapidly. A method of realizing the improved tunnel oxide Q BD using higher post-oxidation time and temperature annealing while at the same time not degrading the quality of subsequent gate oxides is shown. The use of sacrificial oxidation and strip just prior to the transistor gate oxidation is described. This process removes the additional nitride which exists at the field edges, leading to the oxide thinning. As a result, improved tunnel oxide integrity can be achieved without degradation of high and low voltage transistors.
Inventors
- 👤 Timothy K. Carns
- 👤 John A. Smythe, III
- 👤 John A. Ransom
- 👤 Bernice L. Kickel
- 👤 John E. Berg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:51
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; H10B; H10B41/00; H10B41/40; H10B41/42; H10B41/49; H10D64/01344; H10D64/60; H10D64/66; H10D64/68; H10D64/693
Claims Analysis
Total Claims: 45
Claim 1
Independent Claim
123 words
A method of forming circuit elements in at least a first and second non-overlapping regions of an integrated circuit on a semiconductor body, comprising: forming a first oxide layer upon at least a portion of the first region of the semiconductor body; annealing said first oxide layer; sacrificial oxide layer upon at least a portion of the second region of the semiconductor body subsequent to the annealing; forming a mask over at least a portion of said first oxide layer subsequent to forming the sacrificial oxide layer; and etching said sacrificial oxide layer to expose the semiconductor body, wherein the etching of said sacrificial oxide layer is performed while said mask is over said at least a portion of said first oxide layer.
Claim 2
Independent Claim
123 words
A method of forming circuit elements in at least a first and second non-overlapping regions of an integrated circuit on a semiconductor body, comprising: forming a first oxide layer upon at least a portion of the first region of the semiconductor body; annealing said first oxide layer; sacrificial oxide layer upon at least a portion of the second region of the semiconductor body subsequent to the annealing; forming a mask over at least a portion of said first oxide layer subsequent to forming the sacrificial oxide layer; and etching said sacrificial oxide layer to expose the semiconductor body, wherein the etching of said sacrificial oxide layer is performed while said mask is over said at least a portion of said first oxide layer.
Claim 3
Dependent Claim
22 words
The method as recited in claim 1, wherein annealing said first oxide layer comprises an anneal performed under a nitrous oxide ambient.
Claim 4
Dependent Claim
22 words
The method as recited in claim 2, wherein said anneal performed under a nitrous oxide ambient is performed using rapid thermal processing.
Claim 5
Dependent Claim
26 words
The method as recited in claim 3, wherein said nitrous oxide ambient in said rapid thermal processing nitrous oxide annealing consists essentially of nitrous oxide gas.
Claim 6
Dependent Claim
23 words
The method as recited in claim 4, wherein said rapid thermal processing anneal is performed at a temperature greater than 1050 degrees Celsius.
Claim 7
Dependent Claim
23 words
The method as recited in claim 4, wherein said rapid thermal processing anneal is performed for a time period greater than 40 seconds.
Claim 8
Dependent Claim
32 words
The method as recited in claim 4, wherein said rapid thermal processing anneal is performed for a time period greater than 40 seconds and at a temperature greater than 1050 degrees Celsius.
Claim 9
Dependent Claim
20 words
The method as recited in claim 1, wherein said first oxide layer and said semiconductor body are doped with arsenic.
Claim 10
Dependent Claim
31 words
The method as recited in claim 1, further comprising: etching at least a portion of said first oxide layer to reduce the thickness thereof prior to annealing said first oxide layer.
Claim 11
Dependent Claim
40 words
The method as recited in claim 9, further comprising: further growing said first oxide layer, subsequent to etching at least a portion of said first oxide layer to reduce the thickness thereof, and prior to annealing said first oxide layer.
Claim 12
Dependent Claim
21 words
The method as recited in claim 10, wherein said first oxide layer serves as a tunnel oxide of an EEPROM cell.
Claim 13
Dependent Claim
21 words
The method as recited in claim 10, wherein said first oxide layer serves as a tunnel oxide of a trash memory.
Claim 14
Independent Claim
165 words
A method of forming circuit elements in at least a first and second non-overlapping regions of an integrated circuit on a semiconductor body, comprising: forming a first sacrificial oxide layer upon at least a portion of the first region of the semiconductor body; etching said first sacrificial oxide to expose said semiconductor body; forming a first oxide layer upon at least a portion of the first region of the semiconductor body subsequent to etching said first sacrificial oxide; annealing said first oxide layer; forming a second sacrificial oxide layer upon at least a portion of the second region of the semiconductor body subsequent to the annealing; forming a mask over at least a portion of said first oxide layer subsequent to forming said second sacrificial oxide layer; and etching said second sacrificial oxide layer to expose the semiconductor body, wherein the etching of said second sacrificial oxide layer is performed while said mask is over said at least a portion of said first oxide layer.
Claim 15
Independent Claim
165 words
A method of forming circuit elements in at least a first and second non-overlapping regions of an integrated circuit on a semiconductor body, comprising: forming a first sacrificial oxide layer upon at least a portion of the first region of the semiconductor body; etching said first sacrificial oxide to expose said semiconductor body; forming a first oxide layer upon at least a portion of the first region of the semiconductor body subsequent to etching said first sacrificial oxide; annealing said first oxide layer; forming a second sacrificial oxide layer upon at least a portion of the second region of the semiconductor body subsequent to the annealing; forming a mask over at least a portion of said first oxide layer subsequent to forming said second sacrificial oxide layer; and etching said second sacrificial oxide layer to expose the semiconductor body, wherein the etching of said second sacrificial oxide layer is performed while said mask is over said at least a portion of said first oxide layer.
Claim 16
Dependent Claim
22 words
The method as recited in claim 13, wherein annealing said first oxide layer comprises an anneal performed under a nitrous oxide ambient.
Claim 17
Dependent Claim
22 words
The method as recited in claim 14, wherein said anneal performed under a nitrous oxide ambient is performed using rapid thermal processing.
Claim 18
Dependent Claim
26 words
The method as recited in claim 15, wherein said nitrous oxide ambient in said rapid thermal processing nitrous oxide annealing consists essentially of nitrous oxide gas.
Claim 19
Dependent Claim
22 words
The method as recited in claim 16, wherein said rapid thermal processing anneal is performed at temperature greater than 1050 degrees Celsius.
Claim 20
Dependent Claim
22 words
The method as recited in claim 16, wherein said rapid thermal processing anneal is performed for time period greater than 40 seconds.
Claim 21
Dependent Claim
32 words
The method as recited in claim 16, wherein said rapid thermal processing anneal is performed for a time period greater than 40 seconds and at a temperature greater than 1050 degrees Celsius.
Claim 22
Dependent Claim
19 words
The method as recited in claim 13, further comprising: doping through said first oxide layer into said semiconductor body.
Claim 23
Dependent Claim
20 words
The method as recited in claim 20, wherein said first oxide layer and said semiconductor body are doped with arsenic.
Claim 24
Dependent Claim
31 words
The method as recited in claim 13, further comprising: etching at least a portion of said first oxide layer to reduce the thickness thereof prior to annealing said first oxide layer.
Claim 25
Dependent Claim
40 words
The method as recited in claim 22, further comprising: further growing said first oxide layer, subsequent to etching at least a portion of said first oxide layer to reduce the thickness thereof, and prior to annealing said first oxide layer.
Claim 26
Dependent Claim
54 words
The method as recited in claim 23, further comprising, subsequent to annealing the first oxide but prior to forming the second sacrificial oxide: forming a first amorphous silicon layer over at least a portion of said first oxide layer; forming a dielectric layer over at least a portion of said first amorphous silicon layer.
Claim 27
Dependent Claim
52 words
The method as recited in claim 23, further comprising, subsequent to annealing the first oxide but prior to forming the second sacrificial oxide: forming a first polysilicon layer over at least a portion of said first oxide layer; forming a dielectric layer over at least a portion of said first polysilicon layer.
Claim 28
Independent Claim
44 words
The method as recited in either of claims 24 or 25, further comprising, subsequent to etching said second sacrificial oxide layer to expose the semiconductor body: forming a second oxide layer on at least a portion of the second region of the semiconductor body.
Claim 29
Dependent Claim
21 words
The method as recited in claim 26, wherein said first oxide layer serves as a tunnel oxide of an EEPROM cell.
Claim 30
Dependent Claim
21 words
The method as recited in claim 27, wherein said second oxide layer serves as a gate oxide of an NMOS transistor.
Claim 31
Dependent Claim
21 words
The method as recited in claim 27, wherein said second oxide layer serves as a gate oxide of an PMOS transistor.
Claim 32
Dependent Claim
21 words
The method as recited in claim 26, wherein said first oxide layer serves as a tunnel oxide of a flash memory.
Claim 33
Dependent Claim
21 words
The method as recited in claim 30, wherein said second oxide layer serves as a gate oxide of an NMOS transistor.
Claim 34
Dependent Claim
21 words
The method as recited in claim 30, wherein said second oxide layer serves as a gate oxide of an PMOS transistor.
Claim 35
Dependent Claim
41 words
The method as recited in claim 1, further comprising: forming a second oxide layer on at least a portion of the semiconductor body exposed in the second region due to etching said second sacrificial oxide layer to expose the semiconductor body.
Claim 36
Dependent Claim
21 words
The method as recited in claim 33, wherein said second oxide layer serves as a gate oxide of a MOS transistor.
Claim 37
Dependent Claim
26 words
The method as recited in claim 34, wherein said first region is an EEPROM sector, and wherein said second region is a high voltage transistor sector.
Claim 38
Dependent Claim
26 words
The method as recited in claim 34, wherein said first region is an EEPROM sector, and wherein said second region is a low voltage transistor sector.
Claim 39
Independent Claim
188 words
A method of forming circuit elements in at least a first and second non-overlapping regions of an integrated circuit on a semiconductor body, comprising: forming a first sacrificial oxide layer upon at least a portion of the first region of the semiconductor body; etching the first sacrificial oxide to expose said semiconductor body; forming a first oxide layer upon at least a portion of the first region of the semiconductor body subsequent to etching the first sacrificial oxide; annealing said first oxide layer; forming a conductive layer over at least a portion of said first oxide layer subsequent to annealing said first oxide layer; forming a dielectric layer over at least a portion of the conductive layer; forming a second sacrificial oxide layer upon at least a portion of the second region of the semiconductor body subsequent to forming the dielectric layer; forming a mask over the dielectric layer subsequent to forming said second sacrificial oxide layer; and etching said second sacrificial oxide layer to expose the semiconductor body, wherein the etching of said second sacrificial oxide layer is performed while said mask is over the dielectric layer.
Claim 40
Independent Claim
188 words
A method of forming circuit elements in at least a first and second non-overlapping regions of an integrated circuit on a semiconductor body, comprising: forming a first sacrificial oxide layer upon at least a portion of the first region of the semiconductor body; etching the first sacrificial oxide to expose said semiconductor body; forming a first oxide layer upon at least a portion of the first region of the semiconductor body subsequent to etching the first sacrificial oxide; annealing said first oxide layer; forming a conductive layer over at least a portion of said first oxide layer subsequent to annealing said first oxide layer; forming a dielectric layer over at least a portion of the conductive layer; forming a second sacrificial oxide layer upon at least a portion of the second region of the semiconductor body subsequent to forming the dielectric layer; forming a mask over the dielectric layer subsequent to forming said second sacrificial oxide layer; and etching said second sacrificial oxide layer to expose the semiconductor body, wherein the etching of said second sacrificial oxide layer is performed while said mask is over the dielectric layer.
Claim 41
Dependent Claim
40 words
The method as recited in claim 37, further comprising: forming a second oxide layer on at least a portion of the second region of the semiconductor body subsequent to etching said second sacrificial oxide layer to expose the semiconductor body.
Claim 42
Dependent Claim
21 words
The method as recited in claim 38, wherein said second oxide layer serves as a gate oxide of a MOS transistor.
Claim 43
Dependent Claim
26 words
The method as recited in claim 39, wherein said first region is an EEPROM sector, and wherein said second region is a high voltage transistor sector.
Claim 44
Dependent Claim
26 words
The method as recited in claim 39, wherein said first region is an EEPROM sector, and wherein said second region is a low voltage transistor sector.
Claim 45
Dependent Claim
22 words
The method as recited in claim 37, wherein annealing said first oxide layer comprises an anneal performed under a nitrous oxide ambient.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-12-26 | 2004-06-26 | 2004-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-12-26 | 2008-06-26 | 2008-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-12-26 | 2012-06-26 | 2012-12-26 | $7700.00 | Window Closed / Lapsed |