Pattern generator for a semiconductor integrated circuit tester

Claim 2

A test pattern generator for a semiconductor integrated circuit tester, comprising: a first read/write memory for receiving and storing test pattern data in a plurality of blocks, said first read/write memory including DRAM, a second read/write memory for storing checking data in a plurality of units, said second read/write memory including SRAM and each unit of checking data stored in the second read/write memory bearing a predetermined relationship to a corresponding block received by the first read/write memory, at least one sequencer for addressing the first read/write memory for reading the blocks of test pattern data in a predetermined order and addressing the second read/write memory for reading the units of checking data from the second read/write memory, and a validating means for receiving a block of test pattern data read from the first read/write memory and the corresponding unit of checking data read from the second read/write memory and providing an output which indicates whether the unit of checking data is in said predetermined relationship with the block.

Claim 3

A test pattern generator according to claim 1, wherein the first read/write memory includes a DRAM timing interface for temporarily storing test pattern data being written to and read from the DRAM.

Claim 4

A test pattern generator according to claim 2, wherein the DRAM timing interface includes at least one cache.

Claim 5

A test pattern generator according to claim 1, including an interface circuit for receiving the blocks of test pattern data from the first read/write memory and providing from each block at least two sets of test pattern data bits for supplying to a pin electronics circuit in respective test cycles of the tester.

Claim 6

A test pattern generator according to claim 4, wherein the first read/write memory includes a plurality of DRAM chips.

Claim 7

A test pattern generator according to claim 5, wherein the DRAM chips each have a multi-bit data path and the multi-bit data paths are connected in parallel to the interface circuit.

Claim 8

A test pattern generator according to claim 4, wherein the first read/write memory and the interface circuit are embodied in a single application specific integrated circuit.

Claim 9

A test pattern generator according to claim 7, wherein the second read/write memory and at least part of the validating means are embodied in the application specific integrated circuit.

Claim 10

A test pattern generator according to claim 7, including a first sequencer for addressing the first read/write memory and a second sequencer for addressing the second read/write memory and wherein the first sequencer is embodied in the application specific integrated circuit.

Claim 11

A test pattern generator according to claim 1, including a first sequencer for addressing the first read/write memory and a second sequencer for addressing the second read/write memory.

Claim 12

A test pattern generator according to claim 10, wherein the first read/write memory has addresses A 1 -A n and the second read/write memory has addresses A 1 -A n and the first sequencer reads blocks of test pattern data from the first read/write memory within the range A 1 -A n in a predetermined order and the second sequencer reads units of checking data from the second read/write memory within the range A 1 -A n in said predetermined order.

Claim 13

A test pattern generator for a semiconductor integrated circuit tester, comprising: a first read/write memory for receiving and storing test pattern data in a plurality of blocks, a second read/write memory for storing checking data in a plurality of units, wherein each unit of checking data stored in the second read/write memory bears a predetermined relationship to a corresponding block received by the first read/write memory, at least one sequencer for addressing the first read/write memory for reading the blocks of test pattern data in a predetermined order and addressing the second read/write memory for reading the units of checking data from the second read/write memory, and a validating means for receiving a block of test pattern data read from the first read/write memory and the corresponding unit of checking data read from the second read/write memory and providing an output which indicates whether the unit of checking data is in said predetermined relationship with the block, and wherein each unit of checking data is composed of one bit and the validating means includes an XOR tree for reducing the block of test pattern data read from the first read/write memory to a single bit and a comparator for comparing said single bit with the corresponding bit of checking data.

Claim 14

A test pattern generator for a semiconductor integrated circuit tester, comprising: a first read/write memory for receiving and storing test pattern data in a plurality of blocks, a second read/write memory for storing checking data in a plurality of units, wherein each unit of checking data stored in the second read/write memory bears a predetermined relationship to a corresponding block received by the first read/write memory, at least one sequencer for addressing the first read/write memory for reading the blocks of test pattern data in a predetermined order and addressing the second read/write memory for reading the units of checking data from the second read/write memory, and a validating means for receiving a block of test pattern data read from the first read/write memory and the corresponding unit of checking data read from the second read/write memory and providing an output which indicates whether the unit of checking data is in said predetermined relationship with the block, and wherein each unit of checking data is composed of one bit and the validating means includes an XOR tree for reducing the block of test pattern data read from the first read/write memory to a single bit and a comparator for comparing said single bit with the corresponding bit of checking data.

Claim 15

A test pattern generator according to claim 12, including a history register which stores blocks of test pattern data read from the first read/write memory during a plurality of cycles on a first-in-first-out basis such that a block of data is retained in the history register at least until the comparator has compared the single bit derived from the block of data with the corresponding bit of checking data.

Claim 16

A test pattern generator for a semiconductor integrated circuit tester, comprising: at least first and second test pattern generator modules each including a pattern read/write memory for receiving and storing test pattern data in a plurality of blocks, the pattern read/write memory of each module including DRAM, a check read/write memory for storing checking data in a plurality of units, the check read/write memory including SRAM and each unit of checking data stored in the check read/write memory bearing a predetermined relationship to all the blocks stored at corresponding addresses of the pattern read/write memory of each test pattern generator module, at least one sequencer for addressing the pattern read/write memories of the first and second test pattern generator modules each in the same order for reading blocks of test pattern data and for addressing the check read/write memory in the same order as the pattern read/write memories for reading units of checking data from the corresponding addresses of the check read/write memory, a validating means for receiving a unit read from an address of the check read/write memory and blocks of test pattern data read from corresponding addresses of the pattern read/write memory of each test pattern generator module and providing an output which indicates whether the unit is in said predetermined relationship with the blocks.

Claim 17

A test pattern generator for a semiconductor integrated circuit tester, comprising: at least first and second test pattern generator modules each including a pattern read/write memory for receiving and storing test pattern data in a plurality of blocks, the pattern read/write memory of each module including DRAM, a check read/write memory for storing checking data in a plurality of units, the check read/write memory including SRAM and each unit of checking data stored in the check read/write memory bearing a predetermined relationship to all the blocks stored at corresponding addresses of the pattern read/write memory of each test pattern generator module, at least one sequencer for addressing the pattern read/write memories of the first and second test pattern generator modules each in the same order for reading blocks of test pattern data and for addressing the check read/write memory in the same order as the pattern read/write memories for reading units of checking data from the corresponding addresses of the check read/write memory, a validating means for receiving a unit read from an address of the check read/write memory and blocks of test pattern data read from corresponding addresses of the pattern read/write memory of each test pattern generator module and providing an output which indicates whether the unit is in said predetermined relationship with the blocks.

Claim 18

A test pattern generator according to claim 14, wherein the pattern read/write memory of each module includes DRAM and a DRAM timing interface for temporarily storing test pattern data being written to and read from the DRAM.

Claim 19

A test pattern generator according to claim 15, wherein the DRAM timing interface includes at least one cache.

Claim 20

A test pattern generator according to claim 14, wherein each module includes an interface circuit for receiving the blocks of test pattern data from the pattern read/write memory and providing from each block at least one set of test pattern data bits for supplying to a pin electronics circuit in a test cycle of the tester.

Claim 21

A test pattern generator according to claim 17, wherein the interface circuit provides from each block of test pattern data at least two sets of pattern data bits for supplying to the pin electronics circuit in respective test cycles of the tester.

Claim 22

A test pattern generator according to claim 17, wherein the pattern read/write memory of each module includes a plurality of DRAM chips having a multi-bit data path connected to the interface circuit.

Claim 23

A test pattern generator according to claim 19, wherein the DRAM chips are connected in parallel to the interface circuit.

Claim 24

A test pattern generator according to claim 17, wherein the pattern read/write memory and interface circuit of each module are embodied in a single application specific integrated circuit.

Claim 25

A test pattern generator according to claim 21, wherein the check read/write memory and validating means of the module are embodied in the application specific integrated circuit.

Claim 26

A test pattern generator according to claim 21, wherein each module includes a first sequencer for addressing the pattern read/write memory and a second sequencer for addressing the check read/write memory and the first sequencer is embodied in the application specific integrated circuit.

Claim 27

A test pattern generator according to claim 14, wherein each module includes a first sequencer for addressing the pattern read/write memory and the tester includes a second sequencer for addressing the check read/write memory.

Claim 28

A test pattern generator according to claim 24, wherein the pattern read/write memory has addresses A 1 -A n and the check read/write memory has addresses A 1 -A n and the first sequencer reads the blocks of test pattern data from the pattern read/write memory within the range A 1 -A n in a predetermined order and the second sequencer reads units of checking data from the check read/write memory within the range A 1 -A n in said predetermined order.

Claim 29

A test pattern generator for a semiconductor integrated circuit tester, comprising: at least first and second test pattern generator modules each including a pattern read/write memory for receiving and storing test pattern data in a plurality of blocks, a check read/write memory for storing checking data in a plurality of units, wherein each unit of checking data stored in the check read/write memory bears a predetermined relationship to all the blocks stored at corresponding addresses of the pattern read/write memory of each test pattern generator module, at least one sequencer for addressing the pattern read/write memories of the first and second test pattern generator modules each in the same order for reading blocks of test pattern data and for addressing the check read/write memory in the same order as the pattern read/write memories for reading units of checking data from the corresponding addresses of the check read/write memory, a validating means for receiving a unit read from an address of the check read/write memory and blocks of test pattern data read from corresponding addresses of the pattern read/write memory of each test pattern generator module and providing an output which indicates whether the unit is in said predetermined relationship with the blocks, and wherein each unit of checking data is composed of one bit and the validating means includes an XOR tree for reducing the block of test pattern data to a single bit and a comparator for comparing said single bit with the corresponding bit of checking data.

Claim 30

A test pattern generator for a semiconductor integrated circuit tester, comprising: at least first and second test pattern generator modules each including a pattern read/write memory for receiving and storing test pattern data in a plurality of blocks, a check read/write memory for storing checking data in a plurality of units, wherein each unit of checking data stored in the check read/write memory bears a predetermined relationship to all the blocks stored at corresponding addresses of the pattern read/write memory of each test pattern generator module, at least one sequencer for addressing the pattern read/write memories of the first and second test pattern generator modules each in the same order for reading blocks of test pattern data and for addressing the check read/write memory in the same order as the pattern read/write memories for reading units of checking data from the corresponding addresses of the check read/write memory, a validating means for receiving a unit read from an address of the check read/write memory and blocks of test pattern data read from corresponding addresses of the pattern read/write memory of each test pattern generator module and providing an output which indicates whether the unit is in said predetermined relationship with the blocks, and wherein each unit of checking data is composed of one bit and the validating means includes an XOR tree for reducing the block of test pattern data to a single bit and a comparator for comparing said single bit with the corresponding bit of checking data.

Claim 31

A test pattern generator according to claim 26, wherein each module includes a history register which stores blocks of test pattern data read from the pattern read/write memory during a plurality of cycles on a first-in-first-out basis such that a block of data is retained in the history register at least until the comparator has compared the single bit derived from the block of data with the corresponding bit of checking data.

Claim 34

A method according to claim 28, wherein each unit of checking data is composed of a single bit and the step of comparing each block of test pattern data read from the read/write memory with the corresponding unit of checking data includes reducing the block of test pattern data to a single parity bit and comparing the parity bit with the unit of checking data.

Claim 37

A method according to claim 30, wherein each unit of checking data is composed of a single bit.