US5265102A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Test pattern generator
Assignee: Advantest Corp
•
Filing: 1990-06-13
•
Granted: 1993-11-23
•
Expires: 2010-06-13
Abstract
Abstract The present invention is directed to a test pattern generator which generates test patterns for testing semiconductor integrated circuits. A DRAM is employed as a test pattern memory. A control circuit generates an address generating clock, a readout control signal, a refresh control signal and a write clock. An address generating circuit responds to the address generating clock to generate an address for reading out of the DRAM of the test pattern generator. Based on the address and the readout control signal, test patterns are read out from the DRAM of the test pattern generator and then they are written into a FiFo memory by the write clock. On the other hand, test patterns are continuously read out from the FiFo memory in synchronization with a pattern generating clock. The average readout rate from the DRAM, including the refresh period, is selected to be higher than the readout rate from the FiFo memory. When filled with the test patterns, the FiFo memory outputs a full flag signal and the control circuit responds to the full flag signal to stop the generation of the address generating clock, the readout control signal and the write clock and, when the full flag signal is reset, resumes their generation. Hence, even if the DRAM is refreshed at regular time intervals, test patterns can be continuously read out from the FiFo memory.
Inventors
- 👤 Atsushi Saito
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 02:33
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31919
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
209 words
A test pattern generator to generate a test pattern on the basis of stored data in response to a system clock, a start signal and a pattern generating clock, comprising: a control circuit operatively connected to operate in response to the system clock to generate an address generating clock, a readout control signal and a write clock in response to the start signal and a full flag signal and to generate a refresh control signal periodically; an address generating circuit operatively connected to receive the address generating clock from said control circuit to generate an address in response to the address generating clock; test pattern memory having at least one DRAM capable of storage therein of a test pattern, said test pattern memory operatively connected to said control circuit to read out the test pattern in response to the readout control signal from said control circuit and the address from said address generating circuit and to perform a refresh operation in response to the refresh control signal; and a FiFo memory operatively connected to write therein the test pattern from said test pattern memory in response to the test pattern in synchronism with the pattern generating clock and to output the full flag signal when filled with test patterns.
Claim 2
Dependent Claim
209 words
A test pattern generator to generate a test pattern on the basis of stored data in response to a system clock, a start signal and a pattern generating clock, comprising: a control circuit operatively connected to operate in response to the system clock to generate an address generating clock, a readout control signal and a write clock in response to the start signal and a full flag signal and to generate a refresh control signal periodically; an address generating circuit operatively connected to receive the address generating clock from said control circuit to generate an address in response to the address generating clock; test pattern memory having at least one DRAM capable of storage therein of a test pattern, said test pattern memory operatively connected to said control circuit to read out the test pattern in response to the readout control signal from said control circuit and the address from said address generating circuit and to perform a refresh operation in response to the refresh control signal; and a FiFo memory operatively connected to write therein the test pattern from said test pattern memory in response to the test pattern in synchronism with the pattern generating clock and to output the full flag signal when filled with test patterns.
Claim 3
Dependent Claim
82 words
The test pattern generator according to claim 1, wherein, letting the period of the pattern generating clock, the readout period of the test pattern memory and the time for the refresh of the test pattern memory be represented by T 1 , T 2 and T r , respectively, and assuming that the test pattern memory performs the refresh operation every m-th readout therefrom, the period T 1 and T 2 are selected so that the following equation holds: m×T.sub.1 >m×T.sub.2 +T.sub.r.
Claim 4
Dependent Claim
173 words
The test pattern generator according to claim 2, wherein said control circuit includes: timing generating means for generating, in synchronism with the system clock, the address generating clock, the readout control signal and the write clock with the same period T 2 and the refresh control signal with a period m×T 2 +T r ; gate means for gating the address generating clock, the readout control signal and the write clock in response to an enable signal; enable signal generating means for generating the enable signal in response to the start signal; full flag signal detecting means for detecting a leading edge of the full flag signal and for causing said enable signal generating means to stop the generation of the enable signal; full flag edge detecting means for detecting a trailing edge of the full flag signal and for causing said enable signal generating means to generate the enable signal; and enable inhibit means for inhibiting supply of the enable signal to said gate means in response to the refresh control signal.
Claim 5
Dependent Claim
81 words
The test pattern generator according to claim 1, wherein said test pattern memory includes: a plurality of N DRAMs operatively connected to receive in parallel the address from said address generating circuit and to receive in parallel the readout control signal and the refresh control signal from said control circuit, N being an integer equal to or greater than two; and a DRAM multiplexer operatively connected to sequentially provide test patterns from said plurality of N DRAMs to said FiFo memory.
Claim 6
Dependent Claim
120 words
The test pattern generator according to claim 1, wherein said test pattern memory includes a plurality of N DRAMs operatively connected to receive in parallel the address from said address generating circuit and to receive in parallel the readout control signal and the refresh control signal from said control circuit, N being an integer equal to or greater than two; and wherein said FiFo memory includes: a plurality of N FiFo memories operatively connected to write therein the test patterns received from said plurality of N DRAMs in response to a parallel connection of the write clock from said control circuit, and a FiFo multiplexer operatively connected to sequentially provide the test patterns from said plurality of N FiFo memories.
Claim 7
Dependent Claim
66 words
The test pattern generator according to claim 5, wherein said control circuit includes clock generating means for generating N readout clocks and for sequentially and cyclically reading out of said N FiFo memories in synchronism with the pattern generating clock, and select signal generating means for generating a select signal and for sequentially and cyclically switching said FiFo multiplexer in synchronism with the pattern generating clock.
References Cited (Backward Citations)
JPS4896258A
Cited
US3982111A
Cited
JPS59204782A
Cited
JPS59207495A
Cited
US4622668A
Cited
JPS63183696A
Cited
US4827476A
Cited
JPS63265181A
Cited
US4782487A
Cited
US4980888A
Cited
US5127010A
Cited
US5091910A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-22 | 1997-05-24 | 1997-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-22 | 2001-05-24 | 2001-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-22 | 2005-05-24 | 2005-11-23 | $7700.00 | Window Closed / Lapsed |