Pattern generator with extended register programming

Claim 2

An algorithmic pattern generator (APG) in a circuit tester for testing circuits, the circuit tester being of a kind having a main vector memory and a subroutine vector memory for storing test vectors, the APG comprising: a programmable sequencer operating to select instructions for execution by the APG, the sequencer including: a program counter storing a program counter address, sequence control logic coupled to the program counter to receive the program counter addresses, the sequence control logic operating in response to sequence control instructions to select a next address and to cause the next address to be stored in the program counter, instruction memory coupled to receive the program counter addresses from the program counter and coupled to the sequence control logic, the instruction memory storing sequence control instructions and operating to provide sequence control instructions to the sequence control logic in response to the program counter address, the instruction memory further storing pattern instructions and operating to provide pattern instructions to the APG in response to the program counter address; an address generator coupled to receive pattern instructions from the instruction memory, the address generator operating to generate X address signals and Y address signals in response to received pattern instructions; and a data generator coupled to receive signals from the address generator and pattern instructions from the instruction memory, the data generator operating to generate data signals in response to received array signals and pattern instructions; wherein the program counter is coupled to drive a subroutine vector memory control circuit in the circuit tester and operates to provide the program counter address to control operation of the subroutine vector memory.

Claim 3

An algorithmic pattern generator (APG) in a circuit tester for testing circuits, the circuit tester being of a kind having a main vector memory and a subroutine vector memory for storing test vectors, the APG comprising: a programmable sequencer operating to select instructions for execution by the APG, the sequencer including: a program counter storing a program counter address, sequence control logic coupled to the program counter to receive the program counter addresses, the sequence control logic operating in response to sequence control instructions to select a next address and to cause the next address to be stored in the program counter, and instruction memory coupled to receive the program counter addresses from the program counter and coupled to the sequence control logic, the instruction memory storing sequence control instructions and operating to provide sequence control instructions to the sequence control logic in response to the program counter address, the instruction memory further storing pattern instructions and operating to provide pattern instructions to the APG in response to the program counter address, the instruction memory comprising a sequence instruction memory and a pattern instruction memory; the sequence instruction memory being coupled to receive program counter addresses from the program counter and being coupled to the sequence control logic, the sequence instruction memory operating to store sequence control instructions and pattern instruction memory addresses and, in response to program counter addresses, to provide sequence control instructions to the sequence control logic and to provide pattern instruction memory addresses to the pattern instruction memory; the pattern instruction memory being coupled to the sequence instruction memory to receive pattern instruction memory addresses from the sequence instruction memory, and operating to store pattern instructions and, in response to pattern instruction memory addresses, to provide pattern instructions to the APG; an address generator coupled to receive pattern instructions from the instruction memory, the address generator operating to generate X address signals and Y address signals in response to received pattern instructions; and a data generator coupled to receive signals from the address generator and pattern instructions from the instruction memory, the data generator operating to generate data signals in response to received array signals and pattern instructions; wherein the program counter is coupled to drive a subroutine vector memory control circuit in the circuit tester and operates to provide the program counter address to control operation of the subroutine vector memory.

Claim 4

An algorithmic pattern generator (APG) in a circuit tester for testing circuits, the circuit tester being of a kind having a main vector memory and a subroutine vector memory for storing test vectors, the APG comprising: a programmable sequencer operating to select instructions for execution by the APG, the sequencer including: a program counter storing a program counter address, sequence control logic coupled to the program counter to receive the program counter addresses, the sequence control logic operating in response to sequence control instructions to select a next address and to cause the next address to be stored in the program counter, and instruction memory coupled to receive the program counter addresses from the program counter and coupled to the sequence control logic, the instruction memory storing sequence control instructions and operating to provide sequence control instructions to the sequence control logic in response to the program counter address, the instruction memory further storing pattern instructions and operating to provide pattern instructions to the APG in response to the program counter address, the instruction memory comprising a sequence instruction memory and a pattern instruction memory; the sequence instruction memory being coupled to receive program counter addresses from the program counter and being coupled to the sequence control logic, the sequence instruction memory operating to store sequence control instructions and pattern instruction memory addresses and, in response to program counter addresses, to provide sequence control instructions to the sequence control logic and to provide pattern instruction memory addresses to the pattern instruction memory; the pattern instruction memory being coupled to the sequence instruction memory to receive pattern instruction memory addresses from the sequence instruction memory, and operating to store pattern instructions and, in response to pattern instruction memory addresses, to provide pattern instructions to the APG; an address generator coupled to receive pattern instructions from the instruction memory, the address generator operating to generate X address signals and Y address signals in response to received pattern instructions; and a data generator coupled to receive signals from the address generator and pattern instructions from the instruction memory, the data generator operating to generate data signals in response to received array signals and pattern instructions; wherein the program counter is coupled to drive a subroutine vector memory control circuit in the circuit tester and operates to provide the program counter address to control operation of the subroutine vector memory.

Claim 5

In an algorithmic pattern generator for generating test vectors for testing circuits, a programmable sequencer comprising: a pair of linked loop counters comprising a first loop counter and second loop counter; a program counter storing a program counter address; and sequence control logic coupled to the program counter to receive the program counter address, the sequence control logic operating in response to sequence control instructions and including logic to: execute a sequence control instruction to program a first initial value for the first loop counter, execute a sequence control instruction to program a second initial value for the second loop counter, and execute a sequence control instruction to loop to a target program counter address until the pair of linked loop counters is exhausted, wherein the pair counts as a cascaded counter pair with each loop counter running from the counter's programmable initial value to a final value.

Claim 6

In an algorithmic pattern generator for generating test vectors for testing circuits, a programmable sequencer comprising: a pair of linked loop counters comprising a first loop counter and second loop counter; a program counter storing a program counter address; and sequence control logic coupled to the program counter to receive the program counter address, the sequence control logic operating in response to sequence control instructions and including logic to: execute a sequence control instruction to program a first initial value for the first loop counter, execute a sequence control instruction to program a second initial value for the second loop counter, and execute a sequence control instruction to loop to a target program counter address until the pair of linked loop counters is exhausted, wherein the pair counts as a cascaded counter pair with each loop counter running from the counter's programmable initial value to a final value.

Claim 7

The APG of claim 3 wherein the sequence control logic further includes logic to: execute a sequence control instruction to loop to a target program counter address until the first loop counter is exhausted and reset the first loop counter to the first initial value after the first loop counter is exhausted; and execute a sequence control instruction to loop to a target program counter address until the second loop counter is exhausted and reset the second loop counter to the second initial value after the second loop counter is exhausted.

Claim 8

The APG of claim 4 wherein: an instruction to loop to a target address until a loop counter is exhausted operates to test the loop counter and (i) if the loop counter is not zero, jump to the target address and decrement the loop counter, and (ii) if the loop counter is zero, reset the loop counter to its initial value and advance to a next instruction in sequence; and an instruction to loop to a target address on a pair of linked loop counters until the pair is exhausted operates to test the second loop counter in the pair and (i) if the second loop counter is not zero, jump to the target address and decrement the second loop counter, and (ii) if the second loop counter is zero, reset the second loop counter to its initial value and loop to the target address until the first loop counter is exhausted.

Claim 9

The APG of claim 4 wherein: the sequencer includes at least eight loop counters including at least two pair of linked loop counters.

Claim 10

In an algorithmic pattern generator (APG) for generating test vectors for testing circuits, an address generator comprising: registers operating to store Y-related values, including: a Y register and a YI register, the YI register operating as an index register to the Y register, a YREF register and a YRI register, the YRI register operating as an index register to the YREF register, a YMAX register, and a YOFF register; Y address circuitry coupled to the Y, YI, YREF, YRI, YMAX and YOFF registers, the circuitry operating to perform arithmetic and logical operations on the Y, YI, YREF, YRI registers, the result of each operation being masked by the YMAX value from the YMAX register before being stored in the Y, YI, YREF, or YRI registers; and a YOFF adder coupled to the YOFF register and the Y register and operating to compute the Y address as the sum of the YOFF value and the Y value.

Claim 11

In an algorithmic pattern generator (APG) for generating test vectors for testing circuits, an address generator comprising: registers operating to store Y-related values, including: a Y register and a YI register, the YI register operating as an index register to the Y register, a YREF register and a YRI register, the YRI register operating as an index register to the YREF register, a YMAX register, and a YOFF register; Y address circuitry coupled to the Y, YI, YREF, YRI, YMAX and YOFF registers, the circuitry operating to perform arithmetic and logical operations on the Y, YI, YREF, YRI registers, the result of each operation being masked by the YMAX value from the YMAX register before being stored in the Y, YI, YREF, or YRI registers; and a YOFF adder coupled to the YOFF register and the Y register and operating to compute the Y address as the sum of the YOFF value and the Y value.

Claim 12

The address generator of claim 7 further comprising: registers operating to store X-related values, including: an X register and an XI register, the XI register operating as an index register to the X register, an XREF register and an XRI register, the XRI register operating as an index register to the XREF register, an XMAX register, and an XOFF register; X address circuitry coupled to the X, XI, XREF, XRI, XMAX and XOFF registers, the circuitry operating to perform arithmetic and logical operations on the X, XI, XREF, XRI registers, the result of each operation being masked by the XMAX value from the XMAX register before being stored in the X, XI, XREF, or XRI registers; and an XOFF adder coupled to the XOFF register and the X register and operating to compute the X address as the sum of the XOFF value and the X value.

Claim 13

In an algorithmic pattern generator for generating test vectors for testing circuits, a programmable sequencer comprising: a program counter storing a program counter address; sequence control logic coupled to the program counter to receive the program counter addresses, the sequence control logic operating in response to sequence control instructions to select a next address and to cause the next address to be stored in the program counter; instruction memory coupled to receive the program counter addresses from the program counter and coupled to the sequence control logic, the instruction memory storing sequence control instructions and operating to provide sequence control instructions to the sequence control logic in response to the program counter address; a refresh circuit coupled to the sequence control logic, the refresh circuit operating to generate a refresh interrupt signal at a timed interval and to provide the refresh interrupt signal to the sequence control logic, the sequence control logic operating to call a refresh subroutine in instruction memory in response to the refresh interrupt signal.

Claim 14

In an algorithmic pattern generator for generating test vectors for testing circuits, a programmable sequencer comprising: a program counter storing a program counter address; sequence control logic coupled to the program counter to receive the program counter addresses, the sequence control logic operating in response to sequence control instructions to select a next address and to cause the next address to be stored in the program counter; instruction memory coupled to receive the program counter addresses from the program counter and coupled to the sequence control logic, the instruction memory storing sequence control instructions and operating to provide sequence control instructions to the sequence control logic in response to the program counter address; a refresh circuit coupled to the sequence control logic, the refresh circuit operating to generate a refresh interrupt signal at a timed interval and to provide the refresh interrupt signal to the sequence control logic, the sequence control logic operating to call a refresh subroutine in instruction memory in response to the refresh interrupt signal.

Claim 15

The sequencer of claim 9 wherein the refresh circuit comprises: a counter circuit having a terminal for receiving a clocking signal and operating to count from an initial value to a final value in response to the clocking signal and to generate the refresh interrupt signal when the final value is reached.

Claim 16

The sequencer of claim 9 wherein the refresh circuit has a terminal for receiving an inhibit signal generated by an instruction executed in response to the sequencer program counter, the inhibit signal causing the refresh subroutine call to be deferred while the inhibit signal is present.

Claim 17

In an algorithmic pattern generator (APG) for generating test vectors for testing circuits, a data generator comprising: a first stage circuit connected to receive as input address signals and operating to produce an invert value; a crosspoint multiplexer circuit connected to receive as input address signals a number M of address signals and operating to produce as outputs output address signals being a selection of a smaller number m of the input address signals; a topology memory connected to be addressed by the selection of m signals produced as output by the crosspoint multiplexer circuit, the topology memory producing a topology invert bit as output; and a sequence of stages through which the invert value passes serially, an input to the sequence being the output of the first stage circuit, the sequence including as one stage a data inversion gate connected to the topology memory to receive the topology invert bit and operating to invert the invert value according to the state of the topology invert bit.

Claim 18

In an algorithmic pattern generator (APG) for generating test vectors for testing circuits, a data generator comprising: a first stage circuit connected to receive as input address signals and operating to produce an invert value; a crosspoint multiplexer circuit connected to receive as input address signals a number M of address signals and operating to produce as outputs output address signals being a selection of a smaller number m of the input address signals; a topology memory connected to be addressed by the selection of m signals produced as output by the crosspoint multiplexer circuit, the topology memory producing a topology invert bit as output; and a sequence of stages through which the invert value passes serially, an input to the sequence being the output of the first stage circuit, the sequence including as one stage a data inversion gate connected to the topology memory to receive the topology invert bit and operating to invert the invert value according to the state of the topology invert bit.

Claim 19

The data generator of claim 12 wherein: the topology memory is a 2 m ×1 random access memory.

Claim 20

The data generator of claim 12 wherein: the number M is at least 36 and the number m is at least 6.

Claim 21

The data generator of claim 12 further comprising: a latched inversion register coupled to respond to pattern instructions to set and to clear the register, the register providing as output a latched inversion bit; wherein the sequence of stages further includes a stage having a data inversion gate connected to the latched inversion register to receive the latched inversion bit and operating to invert the invert value according to the state of the latched inversion bit.

Claim 22

The data generator of claim 12 wherein the sequence of stages further includes: a delayed access pipeline stage coupled to respond to a DGEN instructions to set a delay length, the delayed access pipeline receiving input data including an invert value and producing as output the input data delayed by a number of APG cycles equal to the delay length; a delay bypass data path bypassing the delayed access pipeline; and wherein both the output of the delayed access pipeline and the output of the delay bypass data path are provided to an output stage of the data generator.

Claim 23

The data generator of claim 16 wherein the delay length is selectable in a range including values from zero to seven.

Claim 24

The data generator of claim 16 wherein input to the delayed access pipeline also includes a shift register control bit and the output of the delayed access pipeline includes the shift register control bit delayed by the delay length.