Pattern generator for cycle delay

Claim 1

A pattern generator for adjusting a delay time of a memory device to be tested, comprising: a first address delay circuit (130) for applying a first address delay time to first address data from an address generation circuit (13), said first address determining a column address of said memory device; a second address delay circuit (170) for applying a second address delay time to second address data from said address generation circuit (13), said second address determining a row address of said memory device; a data delay circuit (140) for applying a data delay time to test data from a data generation circuit (14), said test data provided with said data delay time being applied to said memory device to be tested; and a control signal delay circuit (150) for applying a control delay time to a plurality of control signals from a control signal generation circuit (15), said control signal delay circuit (150) including a selector (153) which selects one or more of said plurality of control signals provided with said control delay time, a delay selection register (154) which provides information to said selector (153) to select said control signals, a cycle delay (151) which provides said control delay time to said control signals, and a delay register (152) which provides information to said cycle delay (151) to determine a length of said control delay time, said control signal selected by said selector being supplied to said memory device to control an operation of said memory device.