Voltage generator for electrically programmable non-volatile memory cells

Claim 2

A three-terminal capacitor adapted to be integrated monolithically to a semiconductor structure, comprising a semiconductor substrate with a first dopant type accommodating an epitaxial well with a second dopant type on whose inside a first diffused region is provided which has a higher concentration of the second dopant type, said epitaxial well being covered by a layer of gate oxide, a first layer of polycrystalline silicon and a further layer of interpoly oxide, and a second layer of polycrystalline silicon, wherein said second layer of polycrystalline silicon comprises a first portion and second portion which are structurally independent and separated one from the other, the second portion in direct contact with the first layer of polycrystalline silicone; and said first portion of the second layer of polycrystalline silicon having a first capacitor contact terminal, said second portion of the second layer of polycrystalline silicon having a second capacitor contact terminal, and said first diffused region having a third capacitor contact terminal.

Claim 3

A capacitor integrated in a semiconductor structure, comprising: a first conductive plate comprising a diffused region in a well of a first conductivity type and having a first capacitor contact terminal; a first dielectric layer of gate oxide formed adjacent to the first conductive plate; a second conductive plate of polycrystalline silicon formed adjacent to the first dielectric layer; a second dielectric layer of interpoly oxide formed adjacent to the second conductive plate; and a third conductive plate of polycrystalline silicon formed adjacent to the second dielectric layer wherein the first dielectric layer is between the first and second conductive plates and the second dielectric layer is between the second and third conductive plate, the third conductive plate comprises a first section having a second capacitor contact terminal and a second section having a third capacitor contact terminal, the first and second sections electrically insulated from each other, and the second section of the third conductive plate being connected to the second conductive plate.

Claim 4

A capacitor integrated in a semiconductor structure, comprising: a first conductive plate comprising a diffused region in a well of a first conductivity type and having a first capacitor contact terminal; a first dielectric layer of gate oxide formed adjacent to the first conductive plate; a second conductive plate of polycrystalline silicon formed adjacent to the first dielectric layer; a second dielectric layer of interpoly oxide formed adjacent to the second conductive plate; and a third conductive plate of polycrystalline silicon formed adjacent to the second dielectric layer wherein the first dielectric layer is between the first and second conductive plates and the second dielectric layer is between the second and third conductive plate, the third conductive plate comprises a first section having a second capacitor contact terminal and a second section having a third capacitor contact terminal, the first and second sections electrically insulated from each other, and the second section of the third conductive plate being connected to the second conductive plate.

Claim 5

A capacitor integrated in a semiconductor structure comprising: a substrate of a first conductivity type; a first diffused region of a second conductivity type formed in an epitaxial well in the substrate, the region forming a first conductive plate; a first layer of oxide adjacent to the region and forming a first dielectric layer; a first layer of polycrystalline silicon adjacent to the first layer of oxide forming a second conductive plate; a second layer of oxide adjacent to the first layer of polycrystalline silicon forming a second dielectric layer; a second layer of polycrystalline silicon adjacent to the second layer of oxide forming a third conductive plate, the second layer of polycrystalline silicon comprising a first portion and a second portion, the first portion being electrically separate from the second portion and the second portion being electrically connected to the first layer of polycrystalline silicon; and a first terminal connected to the region; a second terminal connected to the first portion of the second layer of polycrystalline silicon; and a third terminal connected to the second portion of the second layer of polycrystalline silicon.

Claim 6

A capacitor integrated in a semiconductor structure comprising: a substrate of a first conductivity type; a first diffused region of a second conductivity type formed in an epitaxial well in the substrate, the region forming a first conductive plate; a first layer of oxide adjacent to the region and forming a first dielectric layer; a first layer of polycrystalline silicon adjacent to the first layer of oxide forming a second conductive plate; a second layer of oxide adjacent to the first layer of polycrystalline silicon forming a second dielectric layer; a second layer of polycrystalline silicon adjacent to the second layer of oxide forming a third conductive plate, the second layer of polycrystalline silicon comprising a first portion and a second portion, the first portion being electrically separate from the second portion and the second portion being electrically connected to the first layer of polycrystalline silicon; and a first terminal connected to the region; a second terminal connected to the first portion of the second layer of polycrystalline silicon; and a third terminal connected to the second portion of the second layer of polycrystalline silicon.