Method for fabricating MOS transistor having raised source and drain

Claim 2

A process of fabricating on a substrate a semiconductor device having a raised source, a raised drain and a gate electrode structure, comprising the steps of: forming a plurality of isolation regions on said substrate to isolate a plurality of active regions; forming sequentially a first dielectric layer, a first conductor layer and a second dielectric layer on said substrate; forming on one of said active regions a patterned first resist layer to mask a portion of said second dielectric layer and the underlying first conductor layer and first dielectric layer; removing said second dielectric layer, said first conductor layer and said first dielectric layer other than said portion masked by said first resist layer to form said gate electrode structure; depositing sequentially a third dielectric layer and a fourth dielectric layer on said substrate and said gate electrode structure; removing a top portion of said fourth dielectric layer to expose a portion of said third dielectric layer covering said gate electrode structure; forming on the substrate a patterned second resist layer to mask portions of the fourth dielectric layer; removing said fourth dielectric layer other than said portions masked by said second resist layer to form a plurality of trenches adjacent to said gate electrode structure, wherein portions of the substrate are exposed, and wherein spacers are formed on sidewalls of the gate electrode structure at the same time; filling said plurality of trenches with a second conductor layer, doping said second conductor layer in the trenches with dopants; and driving said dopants into the substrate underneath said trenches to form said raised source and said raised drain.

Claim 3

The process of claim 1, further comprising the step of forming a lightly doped well in said substrate between said step of formation of the isolation regions and said step of formation of the first dielectric layer.

Claim 4

The process of claim 2, wherein said isolation regions are field oxide regions.

Claim 5

The process of claim 3, wherein said step of filling trenches comprises two consecutive steps of: depositing a second conductor layer on said substrate; and removing said second conductor layer other than portions filling said trenches.

Claim 6

The process of claim 4, wherein said step of formation of the raised source and raised drain is carried out in a furnace by annealing.

Claim 7

The process of claim 4, wherein said step of formation of the raised source and raised drain is a rapid thermal processing step.

Claim 8

The process of claim 4, wherein said step of formation of the gate electrode structure is an anisotropic etching step.

Claim 9

The process of claim 4, wherein said step of removing of the second conductor layer is an anisotropic etching step.

Claim 10

The process of claim 1, wherein said first dielectric layer is a CVD silicon oxide layer.

Claim 11

The process of claim 1, wherein said second dielectric layer is a CVD silicon nitride layer.

Claim 12

The process of claim 1, wherein said third dielectric layer is a CVD silicon nitride layer.

Claim 13

The process of claim 1, wherein said fourth dielectric layer is a CVD silicon oxide layer.

Claim 14

The process of claim 1, wherein said second conductor layer is a CVD polysilicon layer.

Claim 15

A process of fabricating on a substrate a semiconductor device having a raised source, a raised drain and a gate electrode structure, comprising the steps of: forming a plurality of isolation regions on said substrate to isolate a plurality of active regions; forming on one of said active regions a gate electrode structure; depositing sequentially a first dielectric layer and a second dielectric layer on said substrate and said gate electrode structure; removing a top portion of said second dielectric layer to expose a portion of said first dielectric layer covering said gate electrode structure; forming on said substrate a patterned resist layer to mask portions of said second dielectric layer; removing said second dielectric layer other than said portions masked by said resist layer to form a plurality of trenches adjacent to said gate electrode structure, wherein portions of the substrate are exposed, and wherein spacers are formed on sidewalls of the gate electrode structure at the same time; filling said plurality of trenches with a first conductor layer; doping said first conductor layer in the trenches with dopants; and driving said dopants into portions of said substrate underneath said trenches to form said raised source and said raised drain.

Claim 16

A process of fabricating on a substrate a semiconductor device having a raised source, a raised drain and a gate electrode structure, comprising the steps of: forming a plurality of isolation regions on said substrate to isolate a plurality of active regions; forming on one of said active regions a gate electrode structure; depositing sequentially a first dielectric layer and a second dielectric layer on said substrate and said gate electrode structure; removing a top portion of said second dielectric layer to expose a portion of said first dielectric layer covering said gate electrode structure; forming on said substrate a patterned resist layer to mask portions of said second dielectric layer; removing said second dielectric layer other than said portions masked by said resist layer to form a plurality of trenches adjacent to said gate electrode structure, wherein portions of the substrate are exposed, and wherein spacers are formed on sidewalls of the gate electrode structure at the same time; filling said plurality of trenches with a first conductor layer; doping said first conductor layer in the trenches with dopants; and driving said dopants into portions of said substrate underneath said trenches to form said raised source and said raised drain.

Claim 17

The process of claim 14, wherein said step of trench filling trenches comprises two consecutive steps of: depositing a first conductor layer on said substrate; and removing said first conductor layer other than portions filling said trenches.

Claim 18

A semiconductor device having a raised source, a raised drain and a gate electrode structure, fabricated on a substrate by a process comprising the steps of: forming a plurality of isolation regions on said substrate to isolate a plurality of active regions; forming sequentially a first dielectric layer, a first conductor layer and a second dielectric layer on said substrate; forming on one of said active regions a patterned first resist layer to mask a portion of said second dielectric layer and the underlying first conductor layer and first dielectric layer; removing said second dielectric layer, said first conductor layer and said first dielectric layer other than said portion masked by said first resist layer to form said gate electrode structure; depositing sequentially a third dielectric layer and a fourth dielectric layer on said substrate and said gate electrode structure; planarizing a top portion of said fourth dielectric layer to expose a portion of said third dielectric layer covering said gate electrode structure; forming on the substrate a patterned second resist layer to mask portions of the fourth dielectric layer; removing said fourth dielectric layer other than said portions masked by said second resist layer to form a plurality of trenches adjacent to said gate electrode structure, wherein portions of the substrate are exposed, and wherein spacers are formed on sidewalls of the gate electrode structure at the same time; filling said plurality of trenches with a second conductor layer; doping said second conductor layer in the trenches with dopants; and driving said dopants into the substrate underneath said trenches to form said raised source and said raised drain.

Claim 19

A semiconductor device having a raised source, a raised drain and a gate electrode structure, fabricated on a substrate by a process comprising the steps of: forming a plurality of isolation regions on said substrate to isolate a plurality of active regions; forming sequentially a first dielectric layer, a first conductor layer and a second dielectric layer on said substrate; forming on one of said active regions a patterned first resist layer to mask a portion of said second dielectric layer and the underlying first conductor layer and first dielectric layer; removing said second dielectric layer, said first conductor layer and said first dielectric layer other than said portion masked by said first resist layer to form said gate electrode structure; depositing sequentially a third dielectric layer and a fourth dielectric layer on said substrate and said gate electrode structure; planarizing a top portion of said fourth dielectric layer to expose a portion of said third dielectric layer covering said gate electrode structure; forming on the substrate a patterned second resist layer to mask portions of the fourth dielectric layer; removing said fourth dielectric layer other than said portions masked by said second resist layer to form a plurality of trenches adjacent to said gate electrode structure, wherein portions of the substrate are exposed, and wherein spacers are formed on sidewalls of the gate electrode structure at the same time; filling said plurality of trenches with a second conductor layer; doping said second conductor layer in the trenches with dopants; and driving said dopants into the substrate underneath said trenches to form said raised source and said raised drain.

Claim 20

The process of claim 16, further comprising the step of forming a lightly doped well in said substrate between said step of formation of the isolation regions and said step of formation of the first dielectric layer.

Claim 21

The process of claim 17, wherein said step of filling trenches comprises two consecutive steps of: depositing a second conductor layer on said substrate; and removing said second conductor layer other than portions filling said trenches.

Claim 22

The semiconductor device of claim 16, wherein said semiconductor device is a MOSFET.

Claim 23

The semiconductor device of claim 16, wherein said semiconductor device is a MOS transistor.