US5773358A
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Method of forming a field effect transistor and method of forming CMOS integrated circuitry
Assignee: Micron Technology Inc
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Filing: 1996-08-12
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Granted: 1998-06-30
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Expires: 2016-08-12
Abstract
Abstract Methods of forming field effect transistors. In one aspect, a method of forming a field effect transistor includes: a) providing a gate structure over a semiconductor substrate, the gate structure comprising a conductively-doped polysilicon region and a dopant masking cap over the conductively-doped polysilicon region; b) providing a layer of polysilicon over the substrate and over the dopant masking cap of the gate structure, the polysilicon layer defining a pair of polysilicon outward projections extending from the semiconductor substrate adjacent the gate structure; c) removing the layer of polysilicon from over the dopant masking cap; d) while the dopant masking cap is over the polysilicon region, conductively doping the pair of polysilicon projections with one of an n-type or a p-type conductivity enhancing dopant impurity; and e) out-diffusing the one of the n-type conductivity enhancing dopant impurity or the p-type conductivity enhancing dopant impurity from the pair of polysilicon projections into the semiconductor substrate to provide one of NMOS or PMOS type diffusion regions, respectively, within the substrate adjacent the gate line.
Inventors
- 👤 Jeff Zhiqiang Wu
- 👤 Sittampalam Yoganathan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:26
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/02; H10D84/03; H10D84/038; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; Y; Y10; Y10S; Y10S148/00; Y10S148/082; Y10S148/141
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
143 words
A method of forming a field effect transistor comprising the following steps: providing a gate over a semiconductor substrate; providing a laver of polysilicon over the substrate, the polysilicon layer defining a pair of polysilicon outward projections extending from the semiconductor substrate adjacent the gate; providing a dopant masking cap over the gate; while the dopant masking cap is over the gate, conductively doping the pair of polysilicon projections with one of an n-type or a p-type conductivity enhancing dopant impurity; providing an outgassing capping layer over the pair of polysilicon; and after providing the outgassing capping layer, out-diffusing the one of the n-type conductivity enhancing dopant impurity or the p-type conductivity enhancing dopant impurity from the pair of polysilicon projections into the semiconductor substrate to provide one of NMOS or PMOS type diffusion regions, respectively. within the substrate adjacent the gate line.
Claim 2
Independent Claim
143 words
A method of forming a field effect transistor comprising the following steps: providing a gate over a semiconductor substrate; providing a laver of polysilicon over the substrate, the polysilicon layer defining a pair of polysilicon outward projections extending from the semiconductor substrate adjacent the gate; providing a dopant masking cap over the gate; while the dopant masking cap is over the gate, conductively doping the pair of polysilicon projections with one of an n-type or a p-type conductivity enhancing dopant impurity; providing an outgassing capping layer over the pair of polysilicon; and after providing the outgassing capping layer, out-diffusing the one of the n-type conductivity enhancing dopant impurity or the p-type conductivity enhancing dopant impurity from the pair of polysilicon projections into the semiconductor substrate to provide one of NMOS or PMOS type diffusion regions, respectively. within the substrate adjacent the gate line.
Claim 3
Independent Claim
138 words
A method of forming a field effect transistor comprising the following steps: providing a gate over a semiconductor substrate; providing a nitride dopant masking cap over the gate; providing oxide insulating sidewall spacers relative to the gate; providing a layer of polysilicon over the substrate, the polysilicon layer defining a pair of polysilicon outward projections extending from the semiconductor substrate adjacent the gate; while the nitride dopant masking cap is over the gate. conductivelv doping the pair of polysilicon projections with one of an n-type or a p-type conductivity enhancing dopant impurity; and out-diffusing the one of the n-type conductivity enhancing dopant impurity or the p-type conductivity enhancing dopant impurity from the pair of polysilicon projections into the semiconductor substrate to provide one of NMOS or PMOS type diffusion regions, respectively, within the substrate adjacent the gate line.
Claim 4
Independent Claim
138 words
A method of forming a field effect transistor comprising the following steps: providing a gate over a semiconductor substrate; providing a nitride dopant masking cap over the gate; providing oxide insulating sidewall spacers relative to the gate; providing a layer of polysilicon over the substrate, the polysilicon layer defining a pair of polysilicon outward projections extending from the semiconductor substrate adjacent the gate; while the nitride dopant masking cap is over the gate. conductivelv doping the pair of polysilicon projections with one of an n-type or a p-type conductivity enhancing dopant impurity; and out-diffusing the one of the n-type conductivity enhancing dopant impurity or the p-type conductivity enhancing dopant impurity from the pair of polysilicon projections into the semiconductor substrate to provide one of NMOS or PMOS type diffusion regions, respectively, within the substrate adjacent the gate line.
Claim 5
Independent Claim
163 words
A method of forming a field effect transistor comprising the following steps: providing a gate over a semiconductor substrate; providing a nitride dopant masking cap over the gate; providing a layer of polysilicon over the substrate, the polysilicon layer defining a pair of polysilicon outward projections extending from the semiconductor substrate adjacent the gate; while the nitride dopant masking cap is over the gate, conductively doping the pair of polvsilicon projections with one of an n-type or a p-type conductivity enhancing dopant impurity; and providing an outgassing capping layer over the pair of polysilicon outward projections; providing oxide insulating sidewall spacers relative to the gate; while the outgassing capping layer is over the pair of polysilicon outward projections, out-diffusing the one of the n-type conductivity enhancing dopant impurity or the p-type conductivity enhancing dopant impurity from the pair of polysilicon projections into the semiconductor substrate to provide one of NMOS or PMOS type diffusion regions, respectively within the substrate adjacent the gate line.
Claim 6
Independent Claim
163 words
A method of forming a field effect transistor comprising the following steps: providing a gate over a semiconductor substrate; providing a nitride dopant masking cap over the gate; providing a layer of polysilicon over the substrate, the polysilicon layer defining a pair of polysilicon outward projections extending from the semiconductor substrate adjacent the gate; while the nitride dopant masking cap is over the gate, conductively doping the pair of polvsilicon projections with one of an n-type or a p-type conductivity enhancing dopant impurity; and providing an outgassing capping layer over the pair of polysilicon outward projections; providing oxide insulating sidewall spacers relative to the gate; while the outgassing capping layer is over the pair of polysilicon outward projections, out-diffusing the one of the n-type conductivity enhancing dopant impurity or the p-type conductivity enhancing dopant impurity from the pair of polysilicon projections into the semiconductor substrate to provide one of NMOS or PMOS type diffusion regions, respectively within the substrate adjacent the gate line.
Claim 7
Independent Claim
158 words
A method of forming a field effect transistor, comprising: providing a gate structure over a semiconductor substrate, the gate structure comprising a conductively-doped polysilicon region and a dopant masking cap over the conductively-doped polysilicon region; providing a layer of polysilicon over the substrate and over the dopant masking cap of the gate structure, the polysilicon layer defining a pair of polysilicon outward projections extending from the semiconductor substrate adjacent the gate structure; removing the layer of polysilicon from over the dopant masking cap; while the dopant masking cap is over the polysilicon region, conductively doping the pair of polysilicon projections with one of an n-type or a p-type conductivity enhancing dopant impurity; and out-diffusing the one of the n-type conductivity enhancing dopant impurity or the p-type conductivity enhancing dopant impurity from the pair of polysilicon projections into the semiconductor substrate to provide one of NMOS or PMOS type diffusion regions, respectively, within the substrate adjacent the gate line.
Claim 8
Independent Claim
158 words
A method of forming a field effect transistor, comprising: providing a gate structure over a semiconductor substrate, the gate structure comprising a conductively-doped polysilicon region and a dopant masking cap over the conductively-doped polysilicon region; providing a layer of polysilicon over the substrate and over the dopant masking cap of the gate structure, the polysilicon layer defining a pair of polysilicon outward projections extending from the semiconductor substrate adjacent the gate structure; removing the layer of polysilicon from over the dopant masking cap; while the dopant masking cap is over the polysilicon region, conductively doping the pair of polysilicon projections with one of an n-type or a p-type conductivity enhancing dopant impurity; and out-diffusing the one of the n-type conductivity enhancing dopant impurity or the p-type conductivity enhancing dopant impurity from the pair of polysilicon projections into the semiconductor substrate to provide one of NMOS or PMOS type diffusion regions, respectively, within the substrate adjacent the gate line.
Claim 9
Dependent Claim
30 words
The method of claim 4 wherein the removing the layer of polysilicon from over the dopant masking cap comprises chemical-mechanical polishing utilizing the dopant masking cap as an etch stop.
Claim 10
Dependent Claim
39 words
The method of claim 4 wherein the removing the layer of polysilicon from over the dopant masking cap comprises chemical-mechanical polishing utilizing the dopant masking cap as an etch stop, and wherein the dopant masking cap comprises silicon nitride.
Claim 11
Dependent Claim
13 words
The method of claim 4 wherein the dopant masking cap comprises silicon nitride.
Claim 12
Dependent Claim
30 words
The method of forming a field effect transistor of claim 4 further comprising providing an outgassing capping layer over the pair of polysilicon outward projections prior to the out-diffusing step.
Claim 13
Dependent Claim
38 words
The method of claim 4 wherein the gate structure further comprises a silicide layer over the doped polysilicon region, and an encapsulating oxide layer over the silicide layer, the encapsulating oxide layer being beneath the dopant masking cap.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-06-29 | 2001-12-29 | 2002-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-29 | 2005-12-29 | 2006-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-29 | 2009-12-29 | 2010-06-30 | $7700.00 | Window Closed / Lapsed |