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US6147996A
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Pipelined multiple issue packet switch
Assignee: Cisco Technology Inc
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Filing: 1995-08-04
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Granted: 2000-11-14
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Expires: 2015-08-04
Abstract
Abstract A pipelined multiple issue architecture for a link layer or protocol layer packet switch, which processes packets independently and asynchronously, but reorders them into their original order, thus preserving the original incoming packet order. Each stage of the pipeline waits for the immediately previous stage to complete, thus causing the packet switch to be self-throttling and thus allowing differing protocols and features to use the same architecture, even if possibly requiring differing processing times. The multiple issue pipeline is scaleable to greater parallel issue of packets, and tunable to differing switch engine architectures, differing interface speeds and widths, and differing clock rates and buffer sizes. The packet switch comprises a fetch stage, which fetches the packet header into one of a plurality of fetch caches, a switching stage comprising a plurality of switch engines, each of which independently and asychronously reads from corresponding fetch caches, makes switching decisions, and write to a reorder memory, a reorder engine which reads from the reorder memory in the packets' original order, and a post-processing stage, comprising a post-process queue and a post-process engine, which performs protocol-specific post-processing on the packets.
Inventors
- 👤 Michael Laor
- 👤 Martin Cieslak
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 22:28
CPC Classifications
H; H04; H04L; H04L49/00; H04L49/90; H04L49/9042; H04L47/00; H04L47/50; H04L47/62; H04L47/622; H04L47/6225; H04L49/30; H04L49/3063; H04L49/901; H04L49/9047; H04L49/3009
Claims Analysis
Total Claims: 65
Claim 1
Independent Claim
158 words
A packet switch comprising a fetch engine coupled to a source of packet headers; a plurality of fetch caches coupled to said fetch engine, and disposed to store at least portions of packet headers received therefrom; a plurality of switch engines, each coupled to a corresponding one of said fetch caches, and disposed to read said portions of packet headers therefrom; a plurality of reorder/rewrite buffers, each said reorder/rewrite buffer coupled to one of said switch engines, and disposed to store pointers to packet headers received from at least one of said plurality of switch engines; a reorder/rewrite engine coupled to said plurality of reorder/rewrite buffers, and disposed to read pointers to packet headers therefrom in an order said packet headers were originally received; a post-process queue coupled to said reorder/rewrite engine, and disposed to store pointers to packet headers received therefrom; and a post-process engine coupled to said post-process queue, and disposed to process said packet headers.
Claim 2
Dependent Claim
158 words
A packet switch comprising a fetch engine coupled to a source of packet headers; a plurality of fetch caches coupled to said fetch engine, and disposed to store at least portions of packet headers received therefrom; a plurality of switch engines, each coupled to a corresponding one of said fetch caches, and disposed to read said portions of packet headers therefrom; a plurality of reorder/rewrite buffers, each said reorder/rewrite buffer coupled to one of said switch engines, and disposed to store pointers to packet headers received from at least one of said plurality of switch engines; a reorder/rewrite engine coupled to said plurality of reorder/rewrite buffers, and disposed to read pointers to packet headers therefrom in an order said packet headers were originally received; a post-process queue coupled to said reorder/rewrite engine, and disposed to store pointers to packet headers received therefrom; and a post-process engine coupled to said post-process queue, and disposed to process said packet headers.
Claim 3
Dependent Claim
98 words
A packet switch comprising: a switching stage; a fetch stage coupled to a source of packet headers, said fetch stage being disposed to fetch at least portions of packet headers and present said portions of packet headers in parallel to said switching stage; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post process stage; and said post-process stage coupled to said switching stage, and being disposed to perform protocol-specific processing on said packet headers.
Claim 4
Dependent Claim
98 words
A packet switch comprising: a switching stage; a fetch stage coupled to a source of packet headers, said fetch stage being disposed to fetch at least portions of packet headers and present said portions of packet headers in parallel to said switching stage; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post process stage; and said post-process stage coupled to said switching stage, and being disposed to perform protocol-specific processing on said packet headers.
Claim 5
Dependent Claim
48 words
A packet switch as in claim 2, wherein said switching stage comprises a plurality of switch engines, each being disposed to receive a packet header and to produce a set of results for switching said packet header such that the input order of said packet header is preserved.
Claim 6
Dependent Claim
146 words
A packet switch, comprising a fetch stage coupled to a source of packet headers, said fetch stage being disposed to fetch at least portions of packet headers and present said portions of packet headers in parallel to a switching stage, wherein said fetch stage comprises a fetch engine, said fetch engine being disposed to fetch a first block of M bytes of a packet header in response to a first signal, and being disposed to fetch an additional block of L bytes of said packet header in response to a second signal; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage; and said post-process stage coupled to said switching stage, and being disposed to perform protocol-specific processing on said packet headers.
Claim 7
Dependent Claim
146 words
A packet switch, comprising a fetch stage coupled to a source of packet headers, said fetch stage being disposed to fetch at least portions of packet headers and present said portions of packet headers in parallel to a switching stage, wherein said fetch stage comprises a fetch engine, said fetch engine being disposed to fetch a first block of M bytes of a packet header in response to a first signal, and being disposed to fetch an additional block of L bytes of said packet header in response to a second signal; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage; and said post-process stage coupled to said switching stage, and being disposed to perform protocol-specific processing on said packet headers.
Claim 8
Dependent Claim
34 words
A packet switch as in claim 4, wherein said first signal indicates an empty fetch cache and wherein said second signal indicates a fetch cache with fewer than a selected number of unread bytes.
Claim 9
Dependent Claim
15 words
A packet switch as in claim 4, wherein M is independent of said packet header.
Claim 10
Dependent Claim
16 words
A packet switch as in claim 4, wherein M is adjusted according to said packet header.
Claim 11
Dependent Claim
24 words
A packet switch as in claim 4, wherein L is equal to a byte width of an interface to said source of packet headers.
Claim 12
Dependent Claim
132 words
A packet switch, comprising a fetch stage coupled to a source of packet headers, said fetch stage being disposed to fetch at least portions of packet headers and present said portions of packet headers in parallel to a switching stage, wherein said fetch stage comprises a plurality of fetch caches, each one of said fetch caches being coupled to said source of packet headers and each being disposed to store at least a portion of a packet header; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage; and said post-process stage coupled to said switching stage, and being disposed to perform protocol-specific processing on said packet headers.
Claim 13
Dependent Claim
132 words
A packet switch, comprising a fetch stage coupled to a source of packet headers, said fetch stage being disposed to fetch at least portions of packet headers and present said portions of packet headers in parallel to a switching stage, wherein said fetch stage comprises a plurality of fetch caches, each one of said fetch caches being coupled to said source of packet headers and each being disposed to store at least a portion of a packet header; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage; and said post-process stage coupled to said switching stage, and being disposed to perform protocol-specific processing on said packet headers.
Claim 14
Dependent Claim
49 words
A packet switch as in claim 9, wherein said switching stage comprises a plurality of switch engines, each being coupled to one said fetch cache and each being disposed to receive said portion of a packet header and to produce a set of results for switching said packet header.
Claim 15
Dependent Claim
197 words
A packet switch, comprising a fetch stage coupled to a source of packet headers, said fetch stage being disposed to fetch at least portions of packet headers and present said portions of packet headers in parallel to a switching stage, wherein said fetch stage comprises a fetch engine coupled to said source of packet headers; a plurality of fetch caches coupled to said fetch engine, each said fetch cache comprising a plurality of buffers; wherein said fetch engine is disposed to write at least a portion of each said packet header in sequence to each said fetch cache in a selected buffer thereof; wherein said switching stage comprises a switch engine for each said fetch cache, wherein each said switch engine is disposed to read at least a portion of said packet header in sequence from each said buffer of said fetch cache; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage; and said post-process stage coupled to said switching stage, and being disposed to perform protocol-specific processing on said packet headers.
Claim 16
Dependent Claim
197 words
A packet switch, comprising a fetch stage coupled to a source of packet headers, said fetch stage being disposed to fetch at least portions of packet headers and present said portions of packet headers in parallel to a switching stage, wherein said fetch stage comprises a fetch engine coupled to said source of packet headers; a plurality of fetch caches coupled to said fetch engine, each said fetch cache comprising a plurality of buffers; wherein said fetch engine is disposed to write at least a portion of each said packet header in sequence to each said fetch cache in a selected buffer thereof; wherein said switching stage comprises a switch engine for each said fetch cache, wherein each said switch engine is disposed to read at least a portion of said packet header in sequence from each said buffer of said fetch cache; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage; and said post-process stage coupled to said switching stage, and being disposed to perform protocol-specific processing on said packet headers.
Claim 17
Dependent Claim
20 words
A packet switch as in claim 11, wherein each said fetch cache is selected for storage in a round-robin manner.
Claim 18
Dependent Claim
120 words
A packet switch, comprising a fetch stage coupled to a source of packet headers, said fetch stage being disposed to fetch at least portions of packet headers and present said portions of packet headers in parallel to a switching stage, wherein said switching stage comprises a plurality of reorder/rewrite memories, each one of said reorder/rewrite memories being disposed to store a pointer to a packet header; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage; and said post-process stage coupled to said switching stage, and being disposed to perform protocol-specific processing on said packet headers.
Claim 19
Dependent Claim
120 words
A packet switch, comprising a fetch stage coupled to a source of packet headers, said fetch stage being disposed to fetch at least portions of packet headers and present said portions of packet headers in parallel to a switching stage, wherein said switching stage comprises a plurality of reorder/rewrite memories, each one of said reorder/rewrite memories being disposed to store a pointer to a packet header; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage; and said post-process stage coupled to said switching stage, and being disposed to perform protocol-specific processing on said packet headers.
Claim 20
Dependent Claim
179 words
A packet switch, comprising a fetch stage coupled to a source of packet headers, said fetch stage being disposed to fetch at least portions of packet headers and present said portions of packet headers in parallel to a switching stage; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage; said post-process stage coupled to said switching stage, and being disposed to perform protocol-specific processing on said packet headers; and wherein said switching stage comprises a plurality of switch engines, each being disposed to receive a packet header and to produce a set of results for switching said packet header; a plurality of reorder/rewrite memories, each one of said reorder/ rewrite memories being disposed to store a packet header; and a reorder/ rewrite processor coupled to said plurality of reorder/ rewrite memories and disposed to receive said packet headers from said reorder/ rewrite memories in an order in which said packet headers were originally received.
Claim 21
Dependent Claim
179 words
A packet switch, comprising a fetch stage coupled to a source of packet headers, said fetch stage being disposed to fetch at least portions of packet headers and present said portions of packet headers in parallel to a switching stage; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage; said post-process stage coupled to said switching stage, and being disposed to perform protocol-specific processing on said packet headers; and wherein said switching stage comprises a plurality of switch engines, each being disposed to receive a packet header and to produce a set of results for switching said packet header; a plurality of reorder/rewrite memories, each one of said reorder/ rewrite memories being disposed to store a packet header; and a reorder/ rewrite processor coupled to said plurality of reorder/ rewrite memories and disposed to receive said packet headers from said reorder/ rewrite memories in an order in which said packet headers were originally received.
Claim 22
Dependent Claim
168 words
A packet switch, comprising a fetch stage coupled to a source of packet headers, said fetch stage being disposed to fetch at least portions of packet headers and present said portions of packet headers in parallel to a switching stage; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage; said post-process stage coupled to said switching stage, and being disposed to perform protocol-specific processing on said packet headers; and wherein said switching stage comprises a plurality of switch engines, each being disposed to receive a packet header and to produce a set of results for switching said packet header; and a plurality of reorder/rewrite memories, each one of said reorder/rewrite memories being disposed to store a packet header; said reorder/rewrite memories being divided into sets, each said set of reorder/rewrite memories being assigned to and receiving outputs from exactly one said switch engine.
Claim 23
Dependent Claim
168 words
A packet switch, comprising a fetch stage coupled to a source of packet headers, said fetch stage being disposed to fetch at least portions of packet headers and present said portions of packet headers in parallel to a switching stage; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage; said post-process stage coupled to said switching stage, and being disposed to perform protocol-specific processing on said packet headers; and wherein said switching stage comprises a plurality of switch engines, each being disposed to receive a packet header and to produce a set of results for switching said packet header; and a plurality of reorder/rewrite memories, each one of said reorder/rewrite memories being disposed to store a packet header; said reorder/rewrite memories being divided into sets, each said set of reorder/rewrite memories being assigned to and receiving outputs from exactly one said switch engine.
Claim 24
Dependent Claim
157 words
A packet switch, comprising a fetch stage coupled to a source of packet headers, said fetch stage being disposed to fetch at least portions of packet headers and present said portions of packet headers in parallel to a switching stage; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage; said post-process stage coupled to said switching stage, and being disposed to perform protocol-specific processing on said packet headers; and wherein said switching stage comprises a plurality of switching engines, each said switching engine having a plurality of reorder/rewrite memories coupled thereto, each said switching engine being disposed to write in sequence to one of said plurality of reorder/rewrite memories; and a reorder/rewrite engine coupled to all said reorder/rewrite memories, said reorder/rewrite engine being disposed to read in sequence from said reorder/rewrite memories.
Claim 25
Dependent Claim
157 words
A packet switch, comprising a fetch stage coupled to a source of packet headers, said fetch stage being disposed to fetch at least portions of packet headers and present said portions of packet headers in parallel to a switching stage; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage; said post-process stage coupled to said switching stage, and being disposed to perform protocol-specific processing on said packet headers; and wherein said switching stage comprises a plurality of switching engines, each said switching engine having a plurality of reorder/rewrite memories coupled thereto, each said switching engine being disposed to write in sequence to one of said plurality of reorder/rewrite memories; and a reorder/rewrite engine coupled to all said reorder/rewrite memories, said reorder/rewrite engine being disposed to read in sequence from said reorder/rewrite memories.
Claim 26
Dependent Claim
26 words
A packet switch as in claim 16, wherein said reorder/rewrite engine is disposed to alter at least portions of packet headers referenced by said reorder/rewrite memories.
Claim 27
Dependent Claim
119 words
A packet switch, comprising a fetch stage coupled to a source of packet headers, said fetch stage being disposed to fetch at least portions of packet headers and present said portions of packet headers in parallel to a switching stage; said switching stage coupled to said fetch stage, said switching stare being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage; said post-process stage coupled to said switching stage, and being disposed to perform protocol-specific processing on said packet headers, wherein said post-process stage comprises a plurality of post-processing memories, each one of said post-processing memories being disposed to store a pointer to a packet header.
Claim 28
Dependent Claim
119 words
A packet switch, comprising a fetch stage coupled to a source of packet headers, said fetch stage being disposed to fetch at least portions of packet headers and present said portions of packet headers in parallel to a switching stage; said switching stage coupled to said fetch stage, said switching stare being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage; said post-process stage coupled to said switching stage, and being disposed to perform protocol-specific processing on said packet headers, wherein said post-process stage comprises a plurality of post-processing memories, each one of said post-processing memories being disposed to store a pointer to a packet header.
Claim 29
Dependent Claim
122 words
A packet switch, comprising a fetch stage coupled to a source of packet headers, said fetch stage being disposed to fetch at least portions of packet headers and present said portions of packet headers in parallel to a switching stage; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage; said post-process stage coupled to said switching stage, and being disposed to perform protocol-specific processing on said packet headers, wherein said post-process stage comprises a post-processor coupled to said switching stage and disposed to alter at least a portion of a packet header responsive to a switching protocol.
Claim 30
Dependent Claim
122 words
A packet switch, comprising a fetch stage coupled to a source of packet headers, said fetch stage being disposed to fetch at least portions of packet headers and present said portions of packet headers in parallel to a switching stage; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage; said post-process stage coupled to said switching stage, and being disposed to perform protocol-specific processing on said packet headers, wherein said post-process stage comprises a post-processor coupled to said switching stage and disposed to alter at least a portion of a packet header responsive to a switching protocol.
Claim 31
Independent Claim
133 words
A system, comprising a packet memory; a plurality of packet switches coupled to said packet memory; a plurality of reorder memories coupled to said plurality of packet switches; and a reorder engine coupled to said plurality of reorder memories and disposed to receive packet headers from said reorder memories in an order in which they were originally received; wherein, each packet switch comprises a fetch stage coupled to said packet memory, said fetch state being disposed to fetch packet headers from said packet memory and present at least portions of packet headers in parallel to a switching stage; and said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage.
Claim 32
Independent Claim
133 words
A system, comprising a packet memory; a plurality of packet switches coupled to said packet memory; a plurality of reorder memories coupled to said plurality of packet switches; and a reorder engine coupled to said plurality of reorder memories and disposed to receive packet headers from said reorder memories in an order in which they were originally received; wherein, each packet switch comprises a fetch stage coupled to said packet memory, said fetch state being disposed to fetch packet headers from said packet memory and present at least portions of packet headers in parallel to a switching stage; and said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage.
Claim 33
Dependent Claim
42 words
A system as in claim 20, wherein said switching stage comprises a plurality of switch engines, each being disposed to receive a packet header and to produce a set of results such that the in-out order of said packet header is preserved.
Claim 34
Independent Claim
189 words
A system, comprising a packet memory; a plurality of reorder memories; a reorder engine coupled to said plurality of reorder memories and disposed to receive packet headers from said reorder memories in an order in which they were originally received; and a plurality of packet switches coupled to said packet memory and said plurality of reorder memories, wherein each one of said plurality of packet switches comprises a fetch stage coupled to said packet memory, said fetch stage being disposed to fetch packet headers from said packet memory and present at least portions of packet headers in parallel to a switching stage, wherein said fetch stage comprises a fetch engine, said fetch engine being disposed to fetch a first block of M bytes of a packet header in response to a first signal, and being disposed to fetch an additional block of L bytes of said packet header in response to a second signal; and said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage.
Claim 35
Independent Claim
189 words
A system, comprising a packet memory; a plurality of reorder memories; a reorder engine coupled to said plurality of reorder memories and disposed to receive packet headers from said reorder memories in an order in which they were originally received; and a plurality of packet switches coupled to said packet memory and said plurality of reorder memories, wherein each one of said plurality of packet switches comprises a fetch stage coupled to said packet memory, said fetch stage being disposed to fetch packet headers from said packet memory and present at least portions of packet headers in parallel to a switching stage, wherein said fetch stage comprises a fetch engine, said fetch engine being disposed to fetch a first block of M bytes of a packet header in response to a first signal, and being disposed to fetch an additional block of L bytes of said packet header in response to a second signal; and said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage.
Claim 36
Dependent Claim
33 words
A system as in claim 22, wherein said first signal indicates an empty fetch cache and wherein said second signal indicates a fetch cache with fewer than a selected number of unread bytes.
Claim 37
Independent Claim
175 words
A system, comprising a packet memory; a plurality of reorder memories; a reorder engine coupled to said plurality of reorder memories and disposed to receive packet headers from said reorder memories in an order in which they were originally received; and a plurality of packet switches coupled to said packet memory and said plurality of reorder memories, wherein each one of said plurality of packet switches comprises a fetch stage coupled to said packet memory said fetch stage being disposed to fetch packet headers from said packet memory and present at least portions of packet headers in parallel to a switching stage, wherein said fetch stage comprises a plurality of fetch caches, each one of said fetch caches being coupled to said source of packet headers and each being disposed to store at least a portion of a packet header; and said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage.
Claim 38
Independent Claim
175 words
A system, comprising a packet memory; a plurality of reorder memories; a reorder engine coupled to said plurality of reorder memories and disposed to receive packet headers from said reorder memories in an order in which they were originally received; and a plurality of packet switches coupled to said packet memory and said plurality of reorder memories, wherein each one of said plurality of packet switches comprises a fetch stage coupled to said packet memory said fetch stage being disposed to fetch packet headers from said packet memory and present at least portions of packet headers in parallel to a switching stage, wherein said fetch stage comprises a plurality of fetch caches, each one of said fetch caches being coupled to said source of packet headers and each being disposed to store at least a portion of a packet header; and said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage.
Claim 39
Dependent Claim
45 words
A system as in claim 24, wherein said switching stage comprises a plurality of switch engines, each being coupled to one said fetch cache and each being disposed to receive a packet header and to produce a set of results for switching said packet header.
Claim 40
Independent Claim
240 words
A system, comprising a packet memory; a plurality of reorder memories; a reorder engine coupled to said plurality of reorder memories and disposed to receive packet headers from said reorder memories in an order in which they were originally received; and a plurality of packet switches coupled to said packet memory and said plurality of reorder memories, wherein each one of said plurality of packet switches comprises a fetch stage coupled to said packet memory said fetch stage being disposed to fetch packet headers from said packet memory and present at least portions of packet headers in parallel to a switching stage, wherein said fetch stage comprises a fetch engine coupled to said source of packet headers; and a plurality of fetch caches coupled to said fetch engine, each said fetch cache comprising a plurality of buffers; wherein said fetch engine is disposed to write at least a portion of each said packet header in sequence from each said fetch cache in a selected buffer thereof; wherein said switching stage comprises a switch engine for each said fetch cache, wherein each said switch engine is disposed to read at least a portion of said packet header in sequence from each said buffer of said fetch cache; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage.
Claim 41
Independent Claim
240 words
A system, comprising a packet memory; a plurality of reorder memories; a reorder engine coupled to said plurality of reorder memories and disposed to receive packet headers from said reorder memories in an order in which they were originally received; and a plurality of packet switches coupled to said packet memory and said plurality of reorder memories, wherein each one of said plurality of packet switches comprises a fetch stage coupled to said packet memory said fetch stage being disposed to fetch packet headers from said packet memory and present at least portions of packet headers in parallel to a switching stage, wherein said fetch stage comprises a fetch engine coupled to said source of packet headers; and a plurality of fetch caches coupled to said fetch engine, each said fetch cache comprising a plurality of buffers; wherein said fetch engine is disposed to write at least a portion of each said packet header in sequence from each said fetch cache in a selected buffer thereof; wherein said switching stage comprises a switch engine for each said fetch cache, wherein each said switch engine is disposed to read at least a portion of said packet header in sequence from each said buffer of said fetch cache; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage.
Claim 42
Independent Claim
217 words
A system, comprising a packet memory; a plurality of reorder memories; a reorder engine coupled to said plurality of reorder memories and disposed to receive packet headers from said reorder memories in an order in which they were originally received; and a plurality of packet switches coupled to said packet memory and said plurality of reorder memories, wherein each one of said plurality of packet switches comprises a fetch stage coupled to said packet memory said fetch stage being disposed to fetch packet headers from said packet memory and present at least portions of packet headers in parallel to a switching stage; wherein said switching stage comprises a plurality of switch engines, each being disposed to receive a packet header and to produce a set of results for switching said packet header; a plurality of reorder/rewrite memories, each one of said reorder/rewrite memories being disposed to store a packet header; and a reorder/rewrite processor coupled to said plurality of reorder/rewrite memories and disposed to receive said packet headers from said reorder/rewrite memories in an order in which said packet headers were originally received; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage.
Claim 43
Independent Claim
217 words
A system, comprising a packet memory; a plurality of reorder memories; a reorder engine coupled to said plurality of reorder memories and disposed to receive packet headers from said reorder memories in an order in which they were originally received; and a plurality of packet switches coupled to said packet memory and said plurality of reorder memories, wherein each one of said plurality of packet switches comprises a fetch stage coupled to said packet memory said fetch stage being disposed to fetch packet headers from said packet memory and present at least portions of packet headers in parallel to a switching stage; wherein said switching stage comprises a plurality of switch engines, each being disposed to receive a packet header and to produce a set of results for switching said packet header; a plurality of reorder/rewrite memories, each one of said reorder/rewrite memories being disposed to store a packet header; and a reorder/rewrite processor coupled to said plurality of reorder/rewrite memories and disposed to receive said packet headers from said reorder/rewrite memories in an order in which said packet headers were originally received; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage.
Claim 44
Dependent Claim
26 words
A system as in claim 27, wherein said reorder/rewrite processor is disposed to alter at least portions of said packet headers referenced by said reorder/rewrite memories.
Claim 45
Independent Claim
211 words
A system, comprising a packet memory; a plurality of reorder memories; a reorder engine coupled to said plurality of reorder memories and disposed to receive packet headers from said reorder memories in an order in which they were originally received; and a plurality of packet switches coupled to said packet memory and said plurality of reorder memories, wherein each one of said plurality of packet switches comprises a fetch stage coupled to said packet memory, said fetch stage being disposed to fetch packet headers from said packet memory and present at least portions of packet headers in parallel to a switching stage; wherein said switching stage comprises a plurality of switch engines, each being disposed to receive a packet header and to produce a set of results for switching said packet header; and a plurality of reorder/rewrite memories, each one of said reorder/rewrite memories being disposed to store a packet header; said reorder/rewrite memories being divided into sets, each said set of reorder/rewrite memories being assigned to and receiving outputs from exactly one said switch engine; and said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage.
Claim 46
Independent Claim
211 words
A system, comprising a packet memory; a plurality of reorder memories; a reorder engine coupled to said plurality of reorder memories and disposed to receive packet headers from said reorder memories in an order in which they were originally received; and a plurality of packet switches coupled to said packet memory and said plurality of reorder memories, wherein each one of said plurality of packet switches comprises a fetch stage coupled to said packet memory, said fetch stage being disposed to fetch packet headers from said packet memory and present at least portions of packet headers in parallel to a switching stage; wherein said switching stage comprises a plurality of switch engines, each being disposed to receive a packet header and to produce a set of results for switching said packet header; and a plurality of reorder/rewrite memories, each one of said reorder/rewrite memories being disposed to store a packet header; said reorder/rewrite memories being divided into sets, each said set of reorder/rewrite memories being assigned to and receiving outputs from exactly one said switch engine; and said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage.
Claim 47
Independent Claim
199 words
A system, comprising a packet memory; a plurality of reorder memories; a reorder engine coupled to said plurality of reorder memories and disposed to receive packet headers from said reorder memories in an order in which they were originally received; and a plurality of packet switches coupled to said packet memory and said plurality of reorder memories wherein each one of said plurality of packet switches comprises a fetch stage coupled to said packet memory said fetch stage being disposed to fetch packet headers from said packet memory and present at least portions of packet headers in parallel to a switching stage; wherein said switching stage comprises a plurality of switching engines, each said switching engine having a plurality of reorder/rewrite memories coupled thereto, each said switching engine being disposed to write in sequence to one of said plurality of reorder/rewrite memories; and a reorder/rewrite engine coupled to all said reorder/rewrite memories, said reorder/rewrite engine being disposed to read in sequence from said reorder/rewrite memories; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage.
Claim 48
Independent Claim
199 words
A system, comprising a packet memory; a plurality of reorder memories; a reorder engine coupled to said plurality of reorder memories and disposed to receive packet headers from said reorder memories in an order in which they were originally received; and a plurality of packet switches coupled to said packet memory and said plurality of reorder memories wherein each one of said plurality of packet switches comprises a fetch stage coupled to said packet memory said fetch stage being disposed to fetch packet headers from said packet memory and present at least portions of packet headers in parallel to a switching stage; wherein said switching stage comprises a plurality of switching engines, each said switching engine having a plurality of reorder/rewrite memories coupled thereto, each said switching engine being disposed to write in sequence to one of said plurality of reorder/rewrite memories; and a reorder/rewrite engine coupled to all said reorder/rewrite memories, said reorder/rewrite engine being disposed to read in sequence from said reorder/rewrite memories; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage.
Claim 49
Independent Claim
162 words
A system, comprising a packet memory; a plurality of reorder memories; a reorder engine coupled to said plurality of reorder memories and disposed to receive packet headers from said reorder memories in an order in which they were originally received; and a plurality of packet switches coupled to said packet memory and said plurality of reorder memories, wherein each one of said plurality of packet switches comprises a fetch stage coupled to said packet memory, said fetch stage being disposed to fetch packet headers from said packet memory and present at least portions of packet headers in parallel to a switching stage; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage, wherein said switching stage comprises a plurality of reorder/rewrite memories, each one of said reorder/rewrite memories being disposed to store a pointer to a packet header.
Claim 50
Independent Claim
162 words
A system, comprising a packet memory; a plurality of reorder memories; a reorder engine coupled to said plurality of reorder memories and disposed to receive packet headers from said reorder memories in an order in which they were originally received; and a plurality of packet switches coupled to said packet memory and said plurality of reorder memories, wherein each one of said plurality of packet switches comprises a fetch stage coupled to said packet memory, said fetch stage being disposed to fetch packet headers from said packet memory and present at least portions of packet headers in parallel to a switching stage; said switching stage coupled to said fetch stage, said switching stage being disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order to a post-process stage, wherein said switching stage comprises a plurality of reorder/rewrite memories, each one of said reorder/rewrite memories being disposed to store a pointer to a packet header.
Claim 51
Independent Claim
71 words
A method of switching packets, said method comprising fetching a sequence of packet headers corresponding to said packets from a source of said packet headers; presenting said packet headers in parallel to a plurality of switch engines; operating said switch engines to switch said packets asynchronously in parallel; presenting switched packet headers in their original order to a post-processor; and operating said post-processor to perform protocol-specific processing on said packet headers.
Claim 52
Independent Claim
71 words
A method of switching packets, said method comprising fetching a sequence of packet headers corresponding to said packets from a source of said packet headers; presenting said packet headers in parallel to a plurality of switch engines; operating said switch engines to switch said packets asynchronously in parallel; presenting switched packet headers in their original order to a post-processor; and operating said post-processor to perform protocol-specific processing on said packet headers.
Claim 53
Independent Claim
112 words
A method of switching packets, said method comprising fetching a sequence of packet headers corresponding to said packets from a source of said packet headers, wherein said step of fetching includes fetching a first block of M bytes of a packet header in response to a first signal and fetching an additional block of L bytes of said packet header in response to a second signal; presenting said packet headers in parallel to a plurality of switch engines; operating said switch engines to switch said packets asynchronously in parallel; presenting switched packet headers in their original order to a post-processor; and operating said post-processor to perform protocol-specific processing on said packet headers.
Claim 54
Independent Claim
112 words
A method of switching packets, said method comprising fetching a sequence of packet headers corresponding to said packets from a source of said packet headers, wherein said step of fetching includes fetching a first block of M bytes of a packet header in response to a first signal and fetching an additional block of L bytes of said packet header in response to a second signal; presenting said packet headers in parallel to a plurality of switch engines; operating said switch engines to switch said packets asynchronously in parallel; presenting switched packet headers in their original order to a post-processor; and operating said post-processor to perform protocol-specific processing on said packet headers.
Claim 55
Dependent Claim
33 words
A method as in claim 33, wherein said first signal indicates an empty fetch cache and wherein said second signal indicates a fetch cache with fewer than a selected number of unread bytes.
Claim 56
Independent Claim
89 words
A method of switching packets, said method comprising fetching a sequence of packet headers corresponding to said packets from a source of said packet headers, wherein said step of fetching includes storing said packet headers in sequence into a plurality of fetch caches; presenting said packet headers in parallel to a plurality of switch engines; operating said switch engines to switch said packets asynchronously in parallel; presenting switched packet headers in their original order to a post-processor; and operating said post-processor to perform protocol-specific processing on said packet headers.
Claim 57
Independent Claim
89 words
A method of switching packets, said method comprising fetching a sequence of packet headers corresponding to said packets from a source of said packet headers, wherein said step of fetching includes storing said packet headers in sequence into a plurality of fetch caches; presenting said packet headers in parallel to a plurality of switch engines; operating said switch engines to switch said packets asynchronously in parallel; presenting switched packet headers in their original order to a post-processor; and operating said post-processor to perform protocol-specific processing on said packet headers.
Claim 58
Independent Claim
89 words
A method of switching packets, said method comprising fetching a sequence of packet headers corresponding to said packets from a source of said packet headers; presenting said packet headers in parallel to a plurality of switch engines, operating said switch engines to switch said packets asynchronously in parallel; presenting switched packet headers in their original order to a post-processor; and operating said post-processor to perform protocol-specific processing on said packet headers wherein said step of operating said post-processor stage comprises altering at least a portion of a packet header.
Claim 59
Independent Claim
89 words
A method of switching packets, said method comprising fetching a sequence of packet headers corresponding to said packets from a source of said packet headers; presenting said packet headers in parallel to a plurality of switch engines, operating said switch engines to switch said packets asynchronously in parallel; presenting switched packet headers in their original order to a post-processor; and operating said post-processor to perform protocol-specific processing on said packet headers wherein said step of operating said post-processor stage comprises altering at least a portion of a packet header.
Claim 60
Independent Claim
115 words
A method of switching packets, said method comprising fetching a sequence of packet headers corresponding to said packets from a source of said packet headers; presenting said packet headers in parallel to a plurality of switch engines; operating said switch engines to switch said packets asynchronously in parallel, wherein said step of operating said switch engines includes coupling each said packet header to a selected fetch cache, coupling each said fetch cache to a selected switch engine, and coupling a set of results from said selected switch engine to a reorder/rewrite memory; presenting switched packet headers in their original order to a post-processor; and operating said post-processor to perform protocol-specific processing on said packet headers.
Claim 61
Independent Claim
115 words
A method of switching packets, said method comprising fetching a sequence of packet headers corresponding to said packets from a source of said packet headers; presenting said packet headers in parallel to a plurality of switch engines; operating said switch engines to switch said packets asynchronously in parallel, wherein said step of operating said switch engines includes coupling each said packet header to a selected fetch cache, coupling each said fetch cache to a selected switch engine, and coupling a set of results from said selected switch engine to a reorder/rewrite memory; presenting switched packet headers in their original order to a post-processor; and operating said post-processor to perform protocol-specific processing on said packet headers.
Claim 62
Dependent Claim
32 words
A method as in claim 37, wherein said reorder/rewrite memories are divided into sets, each said set of reorder/rewrite memories being assigned to and receiving outputs from exactly one said switch engine.
Claim 63
Independent Claim
132 words
A system, including; a packet memory; a plurality of packet switches coupled to said packet memory, wherein each packet switch includes a fetch stage and a switching stage; said fetch stage being coupled to said packet memory and disposed to fetch packet headers from said packet memory and present at least portions of said packet headers in parallel to said switching stage; said switching stage being coupled to said fetch stage and disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order; a plurality of reorder memories coupled to said plurality of packet switches; and a reorder engine coupled to said plurality of reorder memories and disposed to receive packet headers from said reorder memories in an order in which they were originally received.
Claim 64
Independent Claim
132 words
A system, including; a packet memory; a plurality of packet switches coupled to said packet memory, wherein each packet switch includes a fetch stage and a switching stage; said fetch stage being coupled to said packet memory and disposed to fetch packet headers from said packet memory and present at least portions of said packet headers in parallel to said switching stage; said switching stage being coupled to said fetch stage and disposed to switch said packet headers asynchronously in parallel and present said packet headers in their original order; a plurality of reorder memories coupled to said plurality of packet switches; and a reorder engine coupled to said plurality of reorder memories and disposed to receive packet headers from said reorder memories in an order in which they were originally received.
Claim 65
Dependent Claim
43 words
A system as in claim 39, wherein said switching stage comprises of a plurality of switch engines, each being disposed to receive a packet header and to produce a set of results such that the input order of said packet header is mimicked.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-14 | 2004-05-15 | 2004-11-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-14 | 2008-05-15 | 2008-11-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-14 | 2012-05-15 | 2012-11-14 | $7700.00 | Window Closed / Lapsed |