Resequencing device for a node of a cell switching system

Claim 1

Resequencing device (RU) for a node of a cell switching system, each cell comprising a variable number of sub-cells of fixed length, said node comprising a switching network (SW) transmitting said cells with first variable delays, all the sub-cells of a same cell being subjected to a same first delay; said resequencing device (RU) including means for storing all the cells that have been transmitted through said switching network and for then sending them to at least one output of said resequencing device after various waiting delays constituting second delays having expired so that for each cell the sum of said first and said second delay is equal to a predetermined value substantially equal for all said cells; said means including: a buffer memory (BM) for storing the sub-cells of each cell received by said resequencing device; an address memory (FSAM) for storing the address (FSA) of said buffer memory containing the first sub-cell of each cell; means (TSG, IC1, . . . , ICN, CU1) for finding in said address memory the address (FSA') of said buffer memory containing the first sub-cell of a cell when the waiting delay of the cell has expired and when an output which has to send said cell is available; characterized in that said means for finding the address (FSA') of said buffer memory containing the first sub-cell of a cell when the waiting delay has expired includes: a waiting-cell memory (VIM1), addressable by its content, for storing a waiting-cell identifier (TSTP-OA; TSTP-OM) when a cell is stored in said buffer memory (BM); said identifier being stored at an address (FA) identical to the address where the address (FSA) of said first sub-cell is stored in said address memory (FSAM); and said identifier including: the identity (TSTP) of a time slot during which the waiting delay of said cell will expire and the identity (OA; OM) of at least one output to which said cell has to be sent; marker memories (AM1, . . . , AMN) respectively associated with said outputs of said node and means (DEC) for writing therein a marker when a cell is stored in said buffer memory (BM), each stored marker identifying a time slot during which the waiting delay of at least one cell intended to the output associated with said marker memory will expire; means (RL1, . . . , RLN, LC), respectively associated with said marker memories, for reading and deleting a marker corresponding to the oldest time slot among the markers corresponding to waiting delays having expired when the corresponding output is available; and to provide a cell-to-send identifier (TSTP'-OA'; TSTP'-OM') constituted by the identity (TSTP') of the time slot and by the identity (OA'; OM') of the output corresponding to said read marker; means (LC; LC') for applying said cell-to-send identifier (TSTP'-OA'; TSTP'-OM') to a comparison input of said waiting-cell memory (VIM), said memory then providing the addresses (AD1, AD2, AD3) of all the waiting-cell identifiers (TSTP-OA'; TSTP-OM') corresponding to said cell-to-send identifier; and for freeing the locations of said memory (VIM) corresponding to the cells which have no longer to be sent; means (FFO, MX) for successively applying to an address input of said memory (FSAM) of first sub-cells, each address (AD1, AD2, AD3) provided by said waiting-cell memory (VIM) and for reading therein an address (FSA') of a first sub-cell.