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US6147404A
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Dual barrier and conductor deposition in a dual damascene process for semiconductors
Assignee: Advanced Micro Devices Inc
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Filing: 1999-05-24
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Granted: 2000-11-14
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Expires: 2019-05-24
Abstract
Abstract An integrated circuit and a method for manufacturing therefor is provided in which a partial dual damascene deposition is performed to place a barrier, seed, and conductive layer in most of a via between two interconnect channels and then capping the via with a further barrier, seed, conductive layer to prevent electromigration between an interconnect channel and the via.
Inventors
- 👤 Shekhar Pramanick
- 👤 Dirk Brown
- 👤 John A. Iacoponi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:24
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/042; H10W20/043; H10W20/033; H10W20/036; H10W20/40; H10W20/41; H10W20/425; H10W20/435; H10W20/44; H10W20/4403; H10W20/4432; Y; Y10; Y10S; Y10S257/00; Y10S257/915
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
132 words
An integrated circuit, comprising: a semiconductor device; a first dielectric layer formed over said semiconductor device; a conductive material disposed in said first dielectric layer in contact with said semiconductor device; a second dielectric layer disposed over said first dielectric layer; a barrier layer defining a via in said second dielectric layer, said barrier layer in contact with said conductive material; a seed layer lining said barrier layer; a second conductive material over said seed layer in said via and substantially filling said via; a second barrier layer over said second conductive material, said barrier layer defining a channel in said second dielectric layer; a second seed layer lining said second barrier layer; and a third conductive material over said second seed layer and filling said channel in said second dielectric layer.
Claim 2
Dependent Claim
132 words
An integrated circuit, comprising: a semiconductor device; a first dielectric layer formed over said semiconductor device; a conductive material disposed in said first dielectric layer in contact with said semiconductor device; a second dielectric layer disposed over said first dielectric layer; a barrier layer defining a via in said second dielectric layer, said barrier layer in contact with said conductive material; a seed layer lining said barrier layer; a second conductive material over said seed layer in said via and substantially filling said via; a second barrier layer over said second conductive material, said barrier layer defining a channel in said second dielectric layer; a second seed layer lining said second barrier layer; and a third conductive material over said second seed layer and filling said channel in said second dielectric layer.
Claim 3
Dependent Claim
31 words
The integrated circuit as claimed in claim 1 including: a first barrier layer under said conductive material; and a seed layer disposed between said first barrier layer and said conductive material.
Claim 4
Dependent Claim
30 words
The integrated circuit as claimed in claim 1 wherein said barrier layers use materials selected from a group consisting of tantalum, titanium, tungsten, alloys thereof, compounds thereof, and combinations thereof.
Claim 5
Dependent Claim
31 words
The integrated circuit as claimed in claim 1 wherein said seed layers use materials selected from a group consisting of copper, aluminum, silver, gold, alloys thereof, compounds thereof, and combinations thereof.
Claim 6
Dependent Claim
31 words
The integrated circuit as claimed in claim 1 wherein said conductive materials use materials selected from a group consisting of copper, aluminum, silver, gold, alloys thereof, compounds thereof, and combinations thereof.
Claim 7
Dependent Claim
167 words
An integrated circuit, comprising: a semiconductor device; a first dielectric layer formed over said semiconductor device; a conductive material disposed in said first dielectric layer in contact with said semiconductor device; a via dielectric layer disposed over said first dielectric layer, said via dielectric layer having a via opening provided therein and open to said conductive material; a second dielectric layer formed over said via dielectric layer, said second dielectric layer having an opening provided therein and open to said via opening; a barrier layer lining said via opening and said opening in said second dielectric layer, said barrier layer in contact with said conductive material; a seed layer lining said barrier layer; a second conductive material over said seed layer in said via opening substantially filling said via opening; a second barrier layer over said second conductive material; a second seed layer lining said second barrier layer; and a third conductive material over said second seed layer and filling said opening in said second dielectric layer.
Claim 8
Dependent Claim
167 words
An integrated circuit, comprising: a semiconductor device; a first dielectric layer formed over said semiconductor device; a conductive material disposed in said first dielectric layer in contact with said semiconductor device; a via dielectric layer disposed over said first dielectric layer, said via dielectric layer having a via opening provided therein and open to said conductive material; a second dielectric layer formed over said via dielectric layer, said second dielectric layer having an opening provided therein and open to said via opening; a barrier layer lining said via opening and said opening in said second dielectric layer, said barrier layer in contact with said conductive material; a seed layer lining said barrier layer; a second conductive material over said seed layer in said via opening substantially filling said via opening; a second barrier layer over said second conductive material; a second seed layer lining said second barrier layer; and a third conductive material over said second seed layer and filling said opening in said second dielectric layer.
Claim 9
Dependent Claim
31 words
The integrated circuit as claimed in claim 6 including: a first barrier layer under said conductive material; and a seed layer disposed between said first barrier layer and said conductive material.
Claim 10
Dependent Claim
30 words
The integrated circuit as claimed in claim 6 wherein said barrier layers use materials selected from a group consisting of tantalum, titanium, tungsten, alloys thereof, compounds thereof, and combinations thereof.
Claim 11
Dependent Claim
31 words
The integrated circuit as claimed in claim 6 wherein said seed layers use materials selected from a group consisting of copper, aluminum, silver, gold, alloys thereof, compounds thereof, and combinations thereof.
Claim 12
Dependent Claim
31 words
The integrated circuit as claimed in claim 6 wherein said conductive materials use materials selected from a group consisting of copper, aluminum, silver, gold, alloys thereof, compounds thereof, and combinations thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-14 | 2004-05-15 | 2004-11-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-14 | 2008-05-15 | 2008-11-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-14 | 2012-05-15 | 2012-11-14 | $7700.00 | Window Closed / Lapsed |