Test mode activation and data override

Claim 2

A test mode control circuit for a memory device comprising: a power node; a test mode cycle control node; wherein said test mode control circuit is further configured to generate a logic state on said test mode control node when said test mode control circuit is in a test mode of operation for controlling a reset signal used to cause a write or read to said memory device to terminate.

Claim 3

The test mode circuit of claim 1 wherein said test mode control circuit is configured to place said test mode control circuit into a test mode of operation upon detecting a first logic state on said power node, said first logic state being complementary in logic level to a second logic state used to operate said memory device in a normal operating mode.

Claim 4

The test mode control circuit of claim 1 wherein the duration of time that said logic state continues in said logic state is defined by an external timing device.

Claim 5

The test mode control circuit of claim 3 whenever said timing device is an internal clock.

Claim 6

The test mode control circuit of claim 3 wherein said duration of time that said logic state continues in said logic state is longer than said reset signal generated during the normal operating cycle of said memory device.

Claim 7

The test mode control circuit of claim 5 wherein said duration of time that said logic state continues in said logic state is the same duration as the burn-in cycle used to test said memory device under extreme conditions in a burn-in oven.

Claim 8

The test mode circuit of claim 2 wherein said first logic state is ground.

Claim 9

The test mode circuit of claim 2 wherein said first logic state is V CC .

Claim 10

An integrated circuit comprising: an electrical circuit for operation of said integrated circuit in a normal mode of operation; a test mode circuit for operation of the integrated circuit in a test mode of operation; a plurality of pin-outs from the integrated circuit; wherein one of said pin-outs is shared by two signals, a first signal being a signal that is assigned to said pin-out during the normal mode of operation, and said second signal being a signal that is assigned to said pin-out during the test mode of operation, said second signal activating said test mode circuit for operation of the integrated circuit in the test mode of operation.

Claim 11

An integrated circuit comprising: an electrical circuit for operation of said integrated circuit in a normal mode of operation; a test mode circuit for operation of the integrated circuit in a test mode of operation; a plurality of pin-outs from the integrated circuit; wherein one of said pin-outs is shared by two signals, a first signal being a signal that is assigned to said pin-out during the normal mode of operation, and said second signal being a signal that is assigned to said pin-out during the test mode of operation, said second signal activating said test mode circuit for operation of the integrated circuit in the test mode of operation.

Claim 12

The integrated circuit of claim 9 wherein said first signal is a signal that is set to one state in the normal mode of operation of the integrated circuit and said second signal is complementary in logic level to said state.

Claim 13

The integrated circuit of claim 9 wherein said second signal is Vcc.

Claim 14

The integrated circuit of claim 9 wherein said second signal is ground.

Claim 15

A memory device comprising: operational circuitry for operating said memory device in a normal mode of operation; test mode circuitry for operating said memory device in a test mode of operation; and a block reset control circuit connected to said operational circuitry and said test mode circuitry, said block reset control circuit (i) during normal mode of operation generating an operational reset signal, in response to a signal generated by said operational circuitry, to cause a read or write to terminate and to reset said operational circuitry for a subsequent read or write operation and (ii) during test mode of operation generating a test reset signal, in response to a signal generated by said test mode circuitry, to cause a read or write to terminate and to reset said operational circuitry for a subsequent read or write.

Claim 16

A memory device comprising: operational circuitry for operating said memory device in a normal mode of operation; test mode circuitry for operating said memory device in a test mode of operation; and a block reset control circuit connected to said operational circuitry and said test mode circuitry, said block reset control circuit (i) during normal mode of operation generating an operational reset signal, in response to a signal generated by said operational circuitry, to cause a read or write to terminate and to reset said operational circuitry for a subsequent read or write operation and (ii) during test mode of operation generating a test reset signal, in response to a signal generated by said test mode circuitry, to cause a read or write to terminate and to reset said operational circuitry for a subsequent read or write.

Claim 17

The memory device of claim 13 further comprising a plurality of pin-outs.

Claim 18

The memory device of claim 14 wherein one of said pin-outs is shared by two signals, a first being a signal that is assigned to said pin-out during normal mode of operation, and said second signal being a signal that is assigned to said pin-out during the test mode of operation, said second signal activating said test mode circuitry for operation of the memory device in the test mode of operation.

Claim 19

The memory device of claim 15 wherein said first signal is a signal that is set to one state in the normal mode of operation of the memory device and said second signal is complementary in logic level to said state.

Claim 20

The memory device of claim 16 wherein said second signal is V CC .

Claim 21

The memory device of claim 16 wherein said second signal is ground.

Claim 22

The memory device of claim 13 wherein said block reset control circuit comprises: a first NAND gate having as an output a signal responsive to said signal generated by said test circuitry; a second NAND gate having as an output a signal responsive to said signal generated by said operational circuitry; and a third NAND gate having as inputs the gated outputs from said first and second NAND gates, said third NAND gate producing an operational or test reset signal, depending upon the gated outputs from said first and second NAND gates, to cause a read or write to terminate and to reset said operational circuitry for a subsequent read or write mode.

Claim 23

The memory device of claim 19 wherein during normal mode of operation, said third NAND gate is controlled by said output from said second NAND gate in accordance with a signal generated by said operational circuitry thereby causing said third NAND gate to generate said operational reset signal, and during test mode of operation, said third NAND gate is controlled by said output from said first NAND gate in accordance with a signal generated by said test mode circuitry thereby causing said third NAND gate to generate said test reset signal.

Claim 24

The memory device of claim 19 wherein said first NAND gate has as a first input said signal generated by said test mode circuitry and as a second input said signal generated by a clocking means.

Claim 25

The memory device of claim 19 wherein said second NAND gate has as an input a signal generated by a disable circuit, said disable circuit being responsive to said signal generated by said operational circuitry.

Claim 26

The memory device of claim 19 wherein said second NAND gate has as a second input a signal generated by a memory simulation circuit.

Claim 27

The memory device of claim 20 wherein said test mode circuitry is an asynchronous pin input buffer.

Claim 28

The memory device of claim 20 further comprising a plurality of wordlines and wordline drivers.

Claim 29

The memory device of claim 20 further comprising a data input buffer.

Claim 30

The memory device of claim 21 wherein said clocking means is a clock that is internal to said memory device.

Claim 31

The memory device of claim 21 wherein said clocking means is a clock that is external to said memory device.

Claim 32

An integrated circuit memory device comprising: an electrical circuit for operation of said integrated circuit memory device in a normal mode of operation; a test mode circuit for operation of the integrated circuit memory device in a test mode of operation; a plurality of output pins from the integrated circuit memory device; wherein one of said output pins is shared by two signals, a first signal being a signal that is assigned to said output pin during the normal mode of operation, and said second signal being a signal that is assigned to said output pin during the test mode of operation, said second signal activating said test mode circuit for operation of the integrated circuit memory device in the test mode of operation.

Claim 33

An integrated circuit memory device comprising: an electrical circuit for operation of said integrated circuit memory device in a normal mode of operation; a test mode circuit for operation of the integrated circuit memory device in a test mode of operation; a plurality of output pins from the integrated circuit memory device; wherein one of said output pins is shared by two signals, a first signal being a signal that is assigned to said output pin during the normal mode of operation, and said second signal being a signal that is assigned to said output pin during the test mode of operation, said second signal activating said test mode circuit for operation of the integrated circuit memory device in the test mode of operation.

Claim 34

The integrated circuit memory device of claim 29 wherein said first signal is a signal that is set to one state in the normal mode of operation of the integrated circuit and said second signal is complementary in logic level to said state.

Claim 35

The integrated circuit memory device of claim 29 wherein said second signal is Vcc.

Claim 36

The integrated circuit memory device of claim 29 wherein said second signal is ground.