US5440178A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Static test mode noise filter
Assignee: STMicroelectronics lnc USA
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Filing: 1993-11-30
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Granted: 1995-08-08
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Expires: 2013-11-30
Abstract
Abstract According to the present invention, a time filter prevents unintentional static entry into a test mode. Static entry is delayed an appropriate period of time after receipt of the required stimulus to enter the test mode. The delay period is chosen to be longer than transient conditions present in noisy operating environments such that static entry into the test mode is not accidentally triggered. Only when a super voltage condition is applied to an integrated circuit pin for the duration of a predetermined delay time can static entry to a test mode be accomplished. Exit from a test mode occurs immediately after the stimulus is removed. Delay circuitry of the present invention comprises a plurality of transistors, a schmitt trigger, and a delay element, and the delay circuitry determines the value of the predetermined voltage level and the predetermined delay time.
Inventors
- 👤 David C. McClure
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 17:31
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/125; H03K5/1252
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
250 words
Circuitry to delay static entry into a test mode, comprising: an integrated circuit pin; a super voltage which is applied to the integrated circuit pin when static entry into a test mode is desired; and delay circuitry which allows static entry into the test mode after a predetermined delay time if the super voltage applied to the integrated circuit pin stays below a predetermined threshold voltage level for the duration of the predetermined delay time and which allows immediate exit from the test mode, bypassing the predetermined delay time, when the super voltage on the integrated circuit pin rises above the predetermined threshold voltage, causing the delay circuitry to be reset such that subsequent static entry into the test mode occurs only after the super voltage applied to the integrated circuit pin stays below the predetermined threshold voltage for the duration of the predetermined delay time; wherein the delay circuitry comprises a plurality of transistors connected in series between a load device connected to a first power supply and the integrated circuit pin; a detector element, which has an output signal, connected to the load device; a delay element, which has an output signal and introduces a delay equal to the predetermined delay time, connected to the output signal of the detector element; a logic gate which has a first input signal equal to the output signal of the detector element, a second input signal equal to the output signal of the delay element, and a test mode output signal.
Claim 2
Dependent Claim
250 words
Circuitry to delay static entry into a test mode, comprising: an integrated circuit pin; a super voltage which is applied to the integrated circuit pin when static entry into a test mode is desired; and delay circuitry which allows static entry into the test mode after a predetermined delay time if the super voltage applied to the integrated circuit pin stays below a predetermined threshold voltage level for the duration of the predetermined delay time and which allows immediate exit from the test mode, bypassing the predetermined delay time, when the super voltage on the integrated circuit pin rises above the predetermined threshold voltage, causing the delay circuitry to be reset such that subsequent static entry into the test mode occurs only after the super voltage applied to the integrated circuit pin stays below the predetermined threshold voltage for the duration of the predetermined delay time; wherein the delay circuitry comprises a plurality of transistors connected in series between a load device connected to a first power supply and the integrated circuit pin; a detector element, which has an output signal, connected to the load device; a delay element, which has an output signal and introduces a delay equal to the predetermined delay time, connected to the output signal of the detector element; a logic gate which has a first input signal equal to the output signal of the detector element, a second input signal equal to the output signal of the delay element, and a test mode output signal.
Claim 3
Dependent Claim
33 words
The circuitry of claim 1, wherein the plurality of transistors are comprised of a n-channel transistor, whose gate is connected to a second supply voltage, and at least one diode connected p-channel transistor.
Claim 4
Dependent Claim
53 words
The circuitry of claim 2, wherein the predetermined threshold voltage level is equal to -(VTN+|NVTP|+ΔV) volts, where VTN is equal to the threshold voltage of the n-channel transistor, NVTP is equal to the threshold voltage of N diode connected p-channel transistors, and ΔV is equal to the threshold voltage of the detector element.
Claim 5
Dependent Claim
75 words
The circuitry of claim 3, wherein a source/drain of the n-channel transistor is connected to the load device, and said at least one diode connected p-channel transistor includes a first diode connected p-channel transistor which is connected to the n-channel transistor and a second diode connected p-channel transistor which is connected to the first diode connected p-channel transistor and the integrated circuit pin, and wherein the predetermined threshold voltage level is equal to -(VTN+|2VTP|+ΔV) volts.
Claim 6
Dependent Claim
17 words
The circuitry of claim 4, wherein the predetermined threshold voltage level is equal to approximately -3 volts.
Claim 7
Dependent Claim
14 words
The circuitry of claim 1, wherein the detector element is a schmitt trigger element.
Claim 8
Dependent Claim
13 words
The circuitry of claim 1, wherein the load element is a p-channel transistor.
Claim 9
Dependent Claim
16 words
The circuitry of claim 1, wherein the predetermined delay time is greater than approximately 10 nS.
Claim 10
Dependent Claim
250 words
Circuitry to delay static entry into a test mode, comprising: an integrated circuit pin; a super voltage which is applied to the integrated circuit pin when static entry into a test mode is desired; and delay circuitry which allows static entry into the test mode after a predetermined delay time if the super voltage applied to the integrated circuit pin stays above a predetermined threshold voltage for the duration of the predetermined delay time and which allows immediate exit from the test mode, bypassing the predetermined delay time, when the super voltage on the integrated circuit pin falls below the predetermined threshold voltage level, causing the delay circuitry to be reset such that subsequent static entry into the test mode occurs only after the super voltage applied to the integrated circuit pin stays above the predetermined threshold voltage for the duration of the predetermined delay time; wherein the delay circuitry comprises a plurality of transistors connected in series between a load device connected to a first power supply and the integrated circuit pin; a detector element, which has an output signal, connected to the load device; a delay element, which has an output signal and introduces a delay equal to the predetermined delay time, connected to the output signal of the detector element; a logic gate which has a first input signal equal to the output signal of the detector element, a second input signal equal to the output signal of the delay element, and a test mode output signal.
Claim 11
Dependent Claim
250 words
Circuitry to delay static entry into a test mode, comprising: an integrated circuit pin; a super voltage which is applied to the integrated circuit pin when static entry into a test mode is desired; and delay circuitry which allows static entry into the test mode after a predetermined delay time if the super voltage applied to the integrated circuit pin stays above a predetermined threshold voltage for the duration of the predetermined delay time and which allows immediate exit from the test mode, bypassing the predetermined delay time, when the super voltage on the integrated circuit pin falls below the predetermined threshold voltage level, causing the delay circuitry to be reset such that subsequent static entry into the test mode occurs only after the super voltage applied to the integrated circuit pin stays above the predetermined threshold voltage for the duration of the predetermined delay time; wherein the delay circuitry comprises a plurality of transistors connected in series between a load device connected to a first power supply and the integrated circuit pin; a detector element, which has an output signal, connected to the load device; a delay element, which has an output signal and introduces a delay equal to the predetermined delay time, connected to the output signal of the detector element; a logic gate which has a first input signal equal to the output signal of the detector element, a second input signal equal to the output signal of the delay element, and a test mode output signal.
Claim 12
Dependent Claim
33 words
The circuitry of claim 9, wherein the plurality of transistors are comprised of a p-channel transistor, whose gate is connected to a second supply voltage, and at least one diode connected n-channel transistor.
Claim 13
Dependent Claim
61 words
The circuitry of claim 10, wherein the predetermined threshold voltage level is equal to (VCC+|VTP|+NVTN+ΔV) volts, where VCC is equal to the second supply voltage, VTP is equal to the threshold voltage of the p-channel transistor, NVTN is equal to the threshold voltage of N diode connected n-channel transistors, and ΔV is equal to the threshold voltage of the detector element.
Claim 14
Dependent Claim
75 words
The circuitry of claim 11, wherein a source/drain of the p-channel transistor is connected to the load device, and said at least one diode connected n-channel transistor includes a first diode connected n-channel transistor which is connected to the p-channel transistor and a second diode connected n-channel transistor which is connected to the first diode connected n-channel transistor and the integrated circuit pin, and wherein the predetermined threshold voltage level is equal to (VCC+|VTP|+2VTN+ΔV) volts.
Claim 15
Dependent Claim
19 words
The circuitry of claim 12, wherein the predetermined threshold voltage level is equal to approximately 3 volts above VCC.
Claim 16
Dependent Claim
14 words
The circuitry of claim 9, wherein the detector element is a schmitt trigger element.
Claim 17
Dependent Claim
13 words
The circuitry of claim 9, wherein the load element is a n-channel transistor.
Claim 18
Independent Claim
232 words
A method for delaying static entry into a test mode, comprising the steps of: applying a super voltage to an integrated circuit pin; traversing a predetermined delay time determined by delay circuitry: entering a test mode if the super voltage applied to the integrated circuit pin stays below a predetermined threshold voltage level for the duration of the predetermined delay time; and immediately exiting the test mode, by bypassing the predetermined delay time, and resetting the delay circuitry when the super voltage on the integrated circuit pin rises above the predetermined threshold voltage, such that subsequent static entry into the test mode occurs only after the super voltage applied to the integrated circuit pin stays below the predetermined threshold voltage for the duration of the predetermined delay time; wherein the delay circuitry comprises a plurality of transistors connected in series between a load device connected to a first power supply and the integrated circuit pin; a detector element, which has an output signal, connected to the load device; a delay element, which has an output signal and introduces a delay equal to the predetermined delay time, connected to the output signal of the detector element; a logic gate which has a first input signal equal to the output signal of the detector element, a second input signal equal to the output signal of the delay element, and a test mode output signal.
Claim 19
Independent Claim
232 words
A method for delaying static entry into a test mode, comprising the steps of: applying a super voltage to an integrated circuit pin; traversing a predetermined delay time determined by delay circuitry: entering a test mode if the super voltage applied to the integrated circuit pin stays below a predetermined threshold voltage level for the duration of the predetermined delay time; and immediately exiting the test mode, by bypassing the predetermined delay time, and resetting the delay circuitry when the super voltage on the integrated circuit pin rises above the predetermined threshold voltage, such that subsequent static entry into the test mode occurs only after the super voltage applied to the integrated circuit pin stays below the predetermined threshold voltage for the duration of the predetermined delay time; wherein the delay circuitry comprises a plurality of transistors connected in series between a load device connected to a first power supply and the integrated circuit pin; a detector element, which has an output signal, connected to the load device; a delay element, which has an output signal and introduces a delay equal to the predetermined delay time, connected to the output signal of the detector element; a logic gate which has a first input signal equal to the output signal of the detector element, a second input signal equal to the output signal of the delay element, and a test mode output signal.
Claim 20
Dependent Claim
33 words
The circuitry of claim 16, wherein the plurality of transistors are comprised of a n-channel transistor, whose gate is connected to a second supply voltage, and at least one diode connected p-channel transistor.
Claim 21
Dependent Claim
53 words
The circuitry of claim 17, wherein the predetermined threshold voltage level is equal to -(VTN+|NVTP|+ΔV) volts, where VTN is equal to the threshold voltage of the n-channel transistor, NVTP is equal to the threshold voltage of N diode connected p-channel transistors, and ΔV is equal to the threshold voltage of the detector element.
Claim 22
Dependent Claim
75 words
The circuitry of claim 18, wherein a source/drain of the n-channel transistor is connected to the load device, and said at least one diode connected p-channel transistor includes a first diode connected p-channel transistor which is connected to the n-channel transistor and a second diode connected p-channel transistor which is connected to the first diode connected p-channel transistor and the integrated circuit pin, and wherein the predetermined threshold voltage level is equal to -(VTN+|2VTP|+ΔV) volts.
Claim 23
Dependent Claim
17 words
The circuitry of claim 19, wherein the predetermined threshold voltage level is equal to approximately -3 volts.
Claim 24
Dependent Claim
14 words
The circuitry of claim 16, wherein the detector element is a schmitt trigger element.
Claim 25
Dependent Claim
13 words
The circuitry of claim 16, wherein the load element is a p-channel transistor.
Claim 26
Dependent Claim
16 words
The circuitry of claim 16, wherein the predetermined delay time is greater than approximately 10 nS.
Claim 27
Independent Claim
232 words
A method for delaying static entry into a test mode, comprising the steps of: applying a super voltage to an integrated circuit pin; traversing a predetermined delay time determined by delay circuitry; entering a test mode if the super voltage applied to the integrated circuit pin stays above a predetermined threshold voltage level for the duration of the predetermined delay time; and immediately exiting the test mode, by bypassing the predetermined delay time, and resetting the delay circuitry when the super voltage on the integrated circuit pin falls below the predetermined threshold voltage, such that subsequent static entry into the test mode occurs only after the super voltage applied to the integrated circuit pin stays above the predetermined threshold voltage for the duration of the predetermined delay time; wherein the delay circuitry comprises a plurality of transistors connected in series between a load device connected to a first power supply and the integrated circuit pin; a detector element, which has an output signal, connected to the load device; a delay element, which has an output signal and introduces a delay equal to the predetermined delay time, connected to the output signal of the detector element; a logic gate which has a first input signal equal to the output signal of the detector element, a second input signal equal to the output signal of the delay element, and a test mode output signal.
Claim 28
Independent Claim
232 words
A method for delaying static entry into a test mode, comprising the steps of: applying a super voltage to an integrated circuit pin; traversing a predetermined delay time determined by delay circuitry; entering a test mode if the super voltage applied to the integrated circuit pin stays above a predetermined threshold voltage level for the duration of the predetermined delay time; and immediately exiting the test mode, by bypassing the predetermined delay time, and resetting the delay circuitry when the super voltage on the integrated circuit pin falls below the predetermined threshold voltage, such that subsequent static entry into the test mode occurs only after the super voltage applied to the integrated circuit pin stays above the predetermined threshold voltage for the duration of the predetermined delay time; wherein the delay circuitry comprises a plurality of transistors connected in series between a load device connected to a first power supply and the integrated circuit pin; a detector element, which has an output signal, connected to the load device; a delay element, which has an output signal and introduces a delay equal to the predetermined delay time, connected to the output signal of the detector element; a logic gate which has a first input signal equal to the output signal of the detector element, a second input signal equal to the output signal of the delay element, and a test mode output signal.
Claim 29
Dependent Claim
33 words
The circuitry of claim 24, wherein the plurality of transistors are comprised of a p-channel transistor, whose gate is connected to a second supply voltage, and at least one diode connected n-channel transistor.
Claim 30
Dependent Claim
60 words
The circuitry of claim 25, wherein the predetermined threshold voltage level is equal to (VCC+|VTP|+NVTN+ΔV) volts, where VCC is equal to the second supply voltage, VTP is equal to-the threshold voltage of the p-channel transistor, NVTN is equal to the threshold voltage of N diode connected n-channel transistors, and ΔV is equal to the threshold voltage of the detector element.
Claim 31
Dependent Claim
75 words
The circuitry of claim 26, wherein a source/drain of the p-channel transistor is connected to the load device, and said at least one diode connected n-channel transistor includes a first diode connected n-channel transistor which is connected to the p-channel transistor and a second diode connected n-channel transistor which is connected to the first diode connected n-channel transistor and the integrated circuit pin, and wherein the predetermined threshold voltage level is equal to (VCC+|VTP|+2VTN+ΔV) volts.
Claim 32
Dependent Claim
19 words
The circuitry of claim 27, wherein the predetermined threshold voltage level is equal to approximately 3 volts above VCC.
Claim 33
Dependent Claim
14 words
The circuitry of claim 24, wherein the detector element is a schmitt trigger element.
Claim 34
Dependent Claim
13 words
The circuitry of claim 24, wherein the load element is a n-channel transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-08-07 | 1999-02-06 | 1999-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-07 | 2003-02-06 | 2003-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-07 | 2007-02-06 | 2007-08-08 | $7700.00 | Window Closed / Lapsed |