Transient signal suppression circuit

Claim 2

The combination comprising: an input terminal adapted to receive an input signal; means comprising first and second flip-flops coupled to said input terminal for storing in said second flip-flop a signal (SI 1 ) corresponding to the value of said input signal at a time t 1 , and for storing in said first flip-flop a signal (SI 2 ) corresponding to the value of said input signal at a time t 2 , where t 2 is subsequent to t 1 and the interval t 1 to t 2 defines a sampling interval; a set/reset flip flop; and means, coupled between said first and second flip-flops and said set/reset flip-flop, responsive to the signals stored in said first and second flip flops for: (a) placing said set/reset flip-flop in a condition indicative of the value of the input signal stored in said first and second flip-flops when SI 1 is equal to SI 2 ; and (b) maintaining said set/reset flip-flop in the condition it had prior to t 1 when SI 1 is not equal to SI 2 .

Claim 3

The combination as claimed in claim 1 wherein each one of said first and second flip-flops includes a data input, a data output, and a clock input; wherein the data input of said first flip-flop is connected to said input terminal, and wherein the data output of said first flip-flop is connected to the data input of said second flip-flop; and wherein sampling signals comprising a clock signal are applied to said clock input of said first and second flip flops.

Claim 4

The combination as claimed in claim 2 wherein said set/reset flip-flop has a set input, a reset input, and a signal output; and wherein said means coupled between said first and second flip flops and said set/reset flip-flop includes a first logic gate connected between the data outputs of said first and second flip-flop and said set/reset, and a second logic gate connected between the data outputs of said first and second flip-flop and said set/reset input.

Claim 5

The combination as claimed in claim 3 wherein one of said first and second logic gates includes means responsive to a strobing signal for controlling the point in time when the output of said one of said first and second logic gates places the set/reset flip-flop to a desired condition.

Claim 6

The combination comprising: an input terminal adapted to receive an input signal; first and second clocked master-slave flip-flops, each flip-flop having a data input, a data output, and a clock input; means connecting said input terminal to said data input of said first flip flop; means connecting said data output of said first flip-flop to said data input of said second flip-flop; means for applying sampling signals to said clock inputs of said first and second flip-flops; a set/reset flip-flop having a set input, a reset input, and a signal output; comparing means, connected between said data outputs of said first and second flip-flops and the set and reset inputs of said set/reset flip-flop responsive to the binary values of said data outputs for placing said set/reset flip-flop in the set condition when the data outputs of said first and second flip flops are at the same one binary level and placing the set/reset flip-flop in the reset condition when the data outputs of said first and second flip-flops are at the same, other binary level, and for maintaining said set/reset flip-flop undisturbed when the binary values at the data outputs of said first and second flip-flops are not the same.

Claim 7

The combination comprising: an input terminal adapted to receive an input signal; first and second clocked master-slave flip-flops, each flip-flop having a data input, a data output, and a clock input; means connecting said input terminal to said data input of said first flip flop; means connecting said data output of said first flip-flop to said data input of said second flip-flop; means for applying sampling signals to said clock inputs of said first and second flip-flops; a set/reset flip-flop having a set input, a reset input, and a signal output; comparing means, connected between said data outputs of said first and second flip-flops and the set and reset inputs of said set/reset flip-flop responsive to the binary values of said data outputs for placing said set/reset flip-flop in the set condition when the data outputs of said first and second flip flops are at the same one binary level and placing the set/reset flip-flop in the reset condition when the data outputs of said first and second flip-flops are at the same, other binary level, and for maintaining said set/reset flip-flop undisturbed when the binary values at the data outputs of said first and second flip-flops are not the same.

Claim 8

The combination as claimed in claim 5 wherein each one of said first and second flip-flops is responsive to a first phase of said sampling signals applied to its clock input for transferring information from its data input into its master section and to a second phase of said sampling signals for transferring the information from its master section to its slave section and to its data input.

Claim 9

The combination as claimed in claim 6 wherein said comparing means includes a first logic gate connected between said data outputs of said first and second flip-flops and said set input for providing an AND type function; and a second logic gate connected between said data outputs of said first and second flip-flops and said reset-input for producing a NOR type function.

Claim 10

A circuit for producing an output signal of first significance in response to an input signal having a first value for a period greater than T and for producing an output signal of second significance in response to an input signal having a second value for period greater than T, where said period T is defined by the occurrence of a first sampling signal at time t 1 followed by a second sampling signal at time t 2 , comprising: first and second flip-flops, each flip-flop having a data input, a clock input, and an output terminal; means for applying said input signal to the data input of said first flip-flop; means coupling the data input of said second flip-flop to the data output of said first flip-flop; means for applying sampling signals to the clock inputs of said first and second flip-flops at time t 1 and subsequently at time t 2 for storing the value of the input signal at time t 1 in one of said first and second flip-flops and for storing the value of the input signal at time t 2 in the other one of said first and second flip-flops; a set/reset flip-flop having a set-input, a reset-input, and at least one output terminal; and means, coupled between the output terminals of said first and second flip-flops and the set and reset inputs of said set/reset flip-flops, responsive to the contents stored in said first and second flip-flop for either: (a) placing said set/reset flip-flop in the set state or in the reset state corresponding to the input signal being at said first value or at said second value for the interval t 1 -to-t 2 ; or (b) maintaining the state of the set/reset flip-flop undisturbed when the input signal at t 2 has a different value than at t 1 .

Claim 11

A circuit for producing an output signal of first significance in response to an input signal having a first value for a period greater than T and for producing an output signal of second significance in response to an input signal having a second value for period greater than T, where said period T is defined by the occurrence of a first sampling signal at time t 1 followed by a second sampling signal at time t 2 , comprising: first and second flip-flops, each flip-flop having a data input, a clock input, and an output terminal; means for applying said input signal to the data input of said first flip-flop; means coupling the data input of said second flip-flop to the data output of said first flip-flop; means for applying sampling signals to the clock inputs of said first and second flip-flops at time t 1 and subsequently at time t 2 for storing the value of the input signal at time t 1 in one of said first and second flip-flops and for storing the value of the input signal at time t 2 in the other one of said first and second flip-flops; a set/reset flip-flop having a set-input, a reset-input, and at least one output terminal; and means, coupled between the output terminals of said first and second flip-flops and the set and reset inputs of said set/reset flip-flops, responsive to the contents stored in said first and second flip-flop for either: (a) placing said set/reset flip-flop in the set state or in the reset state corresponding to the input signal being at said first value or at said second value for the interval t 1 -to-t 2 ; or (b) maintaining the state of the set/reset flip-flop undisturbed when the input signal at t 2 has a different value than at t 1 .

Claim 12

The combination as claimed in claim 1 wherein said sampling interval is a fixed period.